Commit Graph

322 Commits

Author SHA1 Message Date
zitingguo-ms
e2078627c7
[AN/LT][Fix bug]:enable phy_an_lt_msft attribute on some platforms (#11147) 2022-06-15 17:29:45 -07:00
Richard.Yu
356b51f4d6
[Tunnel PFC][Fix bug] Fix bug and Tests for adding property 'sai_remap_prio_on_tnl_egress' (#11027)
* [Tunnel PFC] Tests for adding property 'sai_remap_prio_on_tnl_egress'

Add tests for adding property 'sai_remap_prio_on_tnl_egress', this
property should only be added in dual tor environment.

Test done:
Run test test_j2files.py

Co-authored-by: richardyu <richardyu@contoso.com>
2022-06-10 11:14:45 -07:00
Neetha John
453504f421
[qos]: Adjust 7260 buffer sizes to accomodate extra lossless queues (#11018)
Why I did it
As part of PCBB changes, we need to enable 2 extra lossless queues. The changes in this PR are done to adjust only the reserved sizes on Th2 for the additional 2 lossless queues
Calculations are done based on 40 downlinks for T1 and 16 uplinks for dual ToR

How to verify it
Verified that the rendering works fine on Th2 dut
Unit tests have been updated to reflect the modified buffer sizes when pcbb is enabled. There are existing testcases that will test the original buffer sizes when pcbb is disabled. With these changes, was able to build sonic-config-engine wheel successfully

Signed-off-by: Neetha John <nejo@microsoft.com>
2022-06-05 22:20:26 -07:00
Richard.Yu
a6c9e195df
[Tunnel PFC] Add property for tunnel PFC (#10962)
* [Tunnel PFC] Add property for tunnel PFC

Replace the config.bcm file with j2 template file
- Add 'sai_remap_prio_on_tnl_egress=1' property when device metadata local
- Host subtype is 'dualtor'
- Change sai.profile foe the new config.bcm.j2
2022-06-05 08:08:36 -07:00
bingwang-ms
1cc602c6af
Add two extra lossless queues for bounced back traffic (#10496)
Signed-off-by: bingwang <bingwang@microsoft.com>

Why I did it
This PR is to add two extra lossless queues for bounced back traffic.
HLD sonic-net/SONiC#950

SKUs include
Arista-7050CX3-32S-C32
Arista-7050CX3-32S-D48C8
Arista-7260CX3-D108C8
Arista-7260CX3-C64
Arista-7260CX3-Q64

How I did it
Update the buffers.json.j2 template and buffers_config.j2 template to generate new BUFFER_QUEUE table.

For T1 devices, queue 2 and queue 6 are set as lossless queues on T0 facing ports.
For T0 devices, queue 2 and queue 6 are set as lossless queues on T1 facing ports.
Queue 7 is added as a new lossy queue as DSCP 48 is mapped to TC 7, and then mapped into Queue 7

How to verify it
Verified by UT
Verified by coping the new template and generate buffer config with sonic-cfggen
2022-06-02 13:03:27 -07:00
bingwang-ms
0c9bbee735
Update qos template to support SYSTEM_DEFAULT table (#10936)
* Update qos template to support SYSTEM_DEFAULT table

Signed-off-by: bingwang <wang.bing@microsoft.com>
2022-06-02 21:48:57 +08:00
Samuel Angebault
912923f47b
[Arista] Update supervisor configurations (#10913)
* Removed unused default_config.json

* Remove asic.conf file from HW SKUs directories as they are not used by upstream code

* Enable dynamic PCI ID identification on Otterlake2

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-05-30 13:34:55 -07:00
Song Yuan
b23ad6748a
[Arista] Add QOS and buffer profiles for SKU Arista-7800R3-48CQM2-C48 (#10752)
* Add QOS and buffer profiles for Arista SKU.

* Add unit test for SKU Arista-7800R3-48CQM2-C48.
2022-05-23 13:50:04 -07:00
Maxime Lorrillere
392899682f
[Arista] Add support for Wolverine linecards (#8887)
Add support for WolverineQCpu, WolverineQCpuMs, WolverineQCpuBk, WolverineQCpuBkMs

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-05-20 14:11:06 -07:00
Samuel Angebault
123f20fea3
[Arista] Add missing configuration files for linecards (#10749)
Why I did it
Fixes some pmon errors/warnings by providing missing configuration files

How I did it
Add missing pcie.yaml and sensors.conf for supported linecards

How to verify it
pcie-check should pass
sensors should display proper sensor names
2022-05-09 11:51:38 -07:00
Song Yuan
a9d5858da1
Fix buffer template for Arista SKU. (#10663)
Why I did it
The buffer pool & profile setting in buffer template was not correct and caused the errors like the following:

ERR swss#orchagent: :- parseReference: malformed reference:[BUFFER_PROFILE|ingress_lossless_profile]. Must not be surrounded by [ ]

How I did it
Fix the buffer pool & profile setting by removing "[]".

How to verify it
Loaded image with this fix in a switch and made sure the error was not seen anymore.
2022-05-02 09:49:42 -07:00
vmittal-msft
ede1e0e889
Adjustment to ingress pool size to accomodate brcm sai (#10694) 2022-04-28 20:39:56 -07:00
zzhiyuan
d19a953e13
[Arista] Add 1x100G over 4 lanes configuration for 7060DX4 (#10655)
Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
2022-04-25 08:11:32 -07:00
bingwang-ms
3fc3259a35
Define qos map AZURE_TUNNEL for QoS remapping of tunnel traffic (#10565)
* Add AZURE_TUNNEL map

Signed-off-by: bingwang <wang.bing@microsoft.com>
2022-04-25 15:06:10 +08:00
vmittal-msft
dd243c1024
Changes to support topology and port speed agnostic switch init for TD3 based platforms (#10587) 2022-04-18 15:19:22 -07:00
Junhua Zhai
04f810a346
[gearbox] use credo sai v0.7.5 (#10578)
The v0.7.5 has bug fix for the support of gearbox port and macsec counters. It also includes a owl firmware update with owl.lz4.fw.1.94.0.bin.

How I did it
Update credo sai url for v0.7.5
Update gearbox_config.json with using firmware owl.lz4.fw.1.94.0.bin instead of owl.lz4.fw.1.92.1.bin

How to verify it
Test gearbox port and macsec counter successfully on A7280.
2022-04-15 10:41:43 -07:00
Oleksandr Kozodoi
8c10c01bd8
Updated format of generating BUFFER_QUEUE in buffers_defaults templates (#9850)
This PR includes necessary changes for correct generating BUFFER_QUEUE values in DB. Changes are based on the schema.md

Why I did it
Change format of generating BUFFER_QUEUE in DB according to schema.md and yang-model.

Old format:
    "BUFFER_QUEUE": {
        "Ethernet0,Ethernet100,Ethernet104,Ethernet108,Ethernet112,Ethernet116,Ethernet12,Ethernet120,Ethernet124,Ethernet16,Ethernet20,Ethernet24,Ethernet28,Ethernet32,Ethernet36,Ethernet4,Ethernet40,Ethernet44,Ethernet48,Ethernet52,Ethernet56,Ethernet60,Ethernet64,Ethernet68,Ethernet72,Ethernet76,Ethernet8,Ethernet80,Ethernet84,Ethernet88,Ethernet92,Ethernet96|queue": {
            "profile": "profile"
        },
        "Ethernet0,Ethernet100,Ethernet104,Ethernet108,Ethernet112,Ethernet116,Ethernet12,Ethernet120,Ethernet124,Ethernet16,Ethernet20,Ethernet24,Ethernet28,Ethernet32,Ethernet36,Ethernet4,Ethernet40,Ethernet44,Ethernet48,Ethernet52,Ethernet56,Ethernet60,Ethernet64,Ethernet68,Ethernet72,Ethernet76,Ethernet8,Ethernet80,Ethernet84,Ethernet88,Ethernet92,Ethernet96|queue": {
            "profile": "profile"
        }
    },
New format:
    "BUFFER_QUEUE": {
        "Ethernet0|queue": {
            "profile": "profile"
        },
        "Ethernet0|queue": {
            "profile": "profile"
        },
        "Ethernet4|queue": {
            "profile": "profile"
        },
        "Ethernet4|queue": {
            "profile": "profile"
        },
        "Ethernet8|queue": {
            "profile": "profile"
        },
        "Ethernet8|queue": {
            "profile": "profile"
        },
        ...
    }
How I did it
Updated structure of buffers_defaults jinja templates.

Signed-off-by: Oleksandr Kozodoi <oleksandrx.kozodoi@intel.com>
2022-04-13 09:11:01 -07:00
byu343
da43edcf3e
[arista] Update serdes tuning values for 7800r3_48cqm2 (#9967)
This update the serdes tuning values for Arista 7800r3_48cqm2. The values are for the optical transceivers.
2022-04-12 15:53:35 -07:00
Nikola Dancejic
f2acf952fb
[device config] Adding configuration for default route fallback (#10465)
* [device config] Adding configuration for default route fallback
* Set sai_tunnel_underlay_route_mode attribute to fallback to default route if more specific route is unavailable.
2022-04-12 14:43:03 -07:00
byu343
58df23e1d7
[arista] Update serdes tuning values for 7280cr3 (#9966) 2022-04-05 09:49:26 -07:00
bingwang-ms
b9dd1df372
Update qos config to clear queues for bounced back traffic (#10176)
* Update qos config to clear queues for bounced back traffic

Signed-off-by: bingwang <bingwang@microsoft.com>
2022-04-05 22:32:25 +08:00
Kostiantyn Yarovyi
bf5f9c2918
[BFN] Update configuration files (#9913)
* [Barefoot] update switch-tna-sai.conf file

* remove deprecated conf files

* [Barefoot] update switch-tna-sai.conf file for Accton wedge100bf_32qs platform

* pdated switch-tna-sai.conf
2022-03-09 09:57:08 +05:30
abdosi
2bfad16ae1
Fix Headroom value for 7260C64 SKU (#10075)
Updated the Headroom value for (100G,5m) in 7260C64 SKU.
2022-02-24 10:06:43 -08:00
gechiang
ddfe87a71a
[BRCMSAI 6.0.0.13-1] Fix Cancun file directory at new location causing TD3 platform boot issue (#9922) 2022-02-07 08:56:06 -08:00
Samuel Angebault
20f7ae853b
Add platform.json configs for all denali SKUs (#9717) 2022-01-20 12:14:44 +05:30
Samuel Angebault
4e72757dd1
[Arista] Change default_sku for 7050QX-32S (#9730) 2022-01-16 07:36:22 +05:30
zzhiyuan
a6d0a27a18
[Arista] Increase switch PCIe timeout for 7060-cx32s (#9248)
Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
Why I did it
Arista 7060 platform has a rare and unreproduceable PCIe timeout that could possibly be solved with increasing the switch PCIe timeout value. To do this we'll call a script for this platform to increase the PCIe timeout on boot-up.

No issues would be expected from the setpci command. From the PCIe spec:

"Software is permitted to change the value in this field at any
time. For Requests already pending when the Completion
Timeout Value is changed, hardware is permitted to use either
the new or the old value for the outstanding Requests, and is
permitted to base the start time for each Request either on when
this value was changed or on when each request was issued. "

How I did it
Add "platform-init" support in swss docker similar to how "hwsku-init" is called, only this would be for any device belonging to a platform. Then the script would reside in device data folder.

Additionally, add pciutils dependency to docker-orchagent so it can run the setpci commands.

How to verify it
On bootup of an Arista 7060, can execute:
lspci -vv -s 01:00.0 | grep -i "devctl2"
In order to check that the timeout has changed.
2021-12-17 08:43:25 -08:00
Samuel Angebault
d499455752
[Arista] Update driver submodules (#9393)
- Use SfpOptoeBase by default to leverage new `sonic_xcvr` refactor
 - Add support for `Woodleaf` product
 - Move `libsfp-eeprom.so` to a different `.deb` package
 - Add new logrotate configuration for arista logs
 - Improve logging mechanism for the drivers (IO loglevel, fix syslog duplicates)
 - Initialize chassis cards in parallel
 - Refactor of `get_change_event` to fix interrupts treated as presence change
2021-12-08 11:33:36 -08:00
Song Yuan
27a6641fb8
[QoS, Buffer template][new HW SKU] Add qos config and buffer profile for Arista SKU (#8380) 2021-12-07 14:14:32 -08:00
byu343
a8cf990879
Add macsec_ipg setting to arista platforms (#9396) 2021-12-06 10:32:43 +08:00
abdosi
5c2423e974
Added 40G {300/40/5m} pg lookup profile for 7260 100G SKU (#9249)
What I did:
Added 40G {300/40/5m} profile for 7260 100G SKU
2021-11-24 18:56:30 -08:00
Prince Sunny
d6c3a9308c
[broadcom]: td2/td3 change cpu cos num to 10 (#9301)
bcm_num_cos=10 forces SDK default to map internal priority 0-7 to COS 0. It is now consistent with other SKUs.
2021-11-17 20:56:46 -08:00
zzhiyuan
989bd9deb0
[Arista] Fix 7060 flex HWSKU SFP ports and Ethernet8/1 (#9173)
* [Arista] Fix 7060 flex HWSKU SFP ports and Ethernet8/1

* [Arista] Fix polarity flips for Arista 7060 on non-leading intfs

Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
2021-11-10 08:46:25 -08:00
gechiang
ef457ab13f
Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9199) 2021-11-09 07:21:57 -08:00
Qi Luo
add9b651b6
Add platform_asic file to each platform folder in sonic-device-data based package (#8542)
#### Why I did it
Add platform_asic file to each platform folder in sonic-device-data package. The file content will be used as the ground truth of mapping from PLATFORM_STRING to switch ASIC family.

One use case of the mapping is to prevent installing a wrong image, which targets for other ASIC platforms. For example, currently we have several ONIE images naming as sonic-*.bin, it's easy to mistakenly install the wrong image. With this mapping built into image, we could fetch the ONIE platform string, and figure out which ASIC it is using, and check we are installing the correct image.

After this PR merged, each platform vendor has to add one mandatory text file  `device/PLATFORM_VENDOR/PLATFORM_STRING/platform_asic`, with the content of the platform's switch ASIC family.

I will update https://github.com/Azure/SONiC/wiki/Porting-Guide after this PR is merged.

You can get a list of the ASIC platforms by `ls -b platform | cat`. Currently the options are
```
barefoot
broadcom
cavium
centec
centec-arm64
generic
innovium
marvell
marvell-arm64
marvell-armhf
mellanox
nephos
p4
vs
```

Also support
```
broadcom-dnx
```

#### How I did it

#### How to verify it
Test one image on DUT. And check the folders under `/usr/share/sonic/device`
2021-10-08 19:27:48 -07:00
byu343
677f31dac3
[arista] Add asic and phy configs for clearwater2ms (#8174)
* Add ASIC configs for clearwater2ms
* Add 100G gearbox configs for clearwater2ms
2021-10-04 19:11:57 -07:00
Ashok Daparthi-Dell
6cbdf11e53
SONIC QOS YANG - Remove qos tables field value refernce format (#7752)
Depends on Azure/sonic-utilities#1626
Depends on Azure/sonic-swss#1754

QOS tables in config db used ABNF format i.e "[TABLE_NAME|name] to refer fieldvalue to other qos tables.

Example:
Config DB:
"Ethernet92|3": {
"scheduler": "[SCHEDULER|scheduler.1]",
"wred_profile": "[WRED_PROFILE|AZURE_LOSSLESS]"
},
"Ethernet0|0": {
"profile": "[BUFFER_PROFILE|ingress_lossy_profile]"
},
"Ethernet0": {
"dscp_to_tc_map": "[DSCP_TO_TC_MAP|AZURE]",
"pfc_enable": "3,4",
"pfc_to_queue_map": "[MAP_PFC_PRIORITY_TO_QUEUE|AZURE]",
"tc_to_pg_map": "[TC_TO_PRIORITY_GROUP_MAP|AZURE]",
"tc_to_queue_map": "[TC_TO_QUEUE_MAP|AZURE]"
},

This format is not consistent with other DB schema followed in sonic.
And also this reference in DB is not required, This is taken care by YANG "leafref".

Removed this format from all platform files to consistent with other sonic db schema.
Example:
"Ethernet92|3": {
"scheduler": "scheduler.1",
"wred_profile": "AZURE_LOSSLESS"
},

Dependent pull requests:
#7752 - To modify platfrom files
#7281 - Yang model
Azure/sonic-utilities#1626 - DB migration
Azure/sonic-swss#1754 - swss change to remove ABNF format
2021-09-28 09:21:24 -07:00
Samuel Angebault
f899a82864
[Arista] Fix Clearwater2 phy initialization when no configuration is provided (#8271)
Why I did it
Fix an issue on the Clearwater2 linecard.
When the linecard is started with a fresh image without configuration, phys would not be initialized.

How I did it
Added default_sku for Clearwater2 which prevents config-setup from failing to create a default config_db.json.
Added some extra logic in the phy-credo-init script to run the phy_config.sh of the hwsku pointed by default_sku if the DEVICE_METADATA.localhost.hwsku information is not populated in CONFIG_DB.

How to verify it
Booting an image with this change and without configuration will lead to the phys being initialized using the phy_config.sh from default_sku.
2021-09-09 13:03:22 -07:00
Samuel Angebault
2e4f473237
[Arista] Update platform library submodules (#8594)
- Disable health monitoring of `psu.voltage` until support is implemented
 - chassis: disable provisioning bit once linecard has booted
 - chassis: fix issue in `show version` when running as `admin`
 - chassis: fix race when reading an eeprom before it's available
 - chassis: implement `get_all_asics` call
 - api: fix `ChassisBase.get_system_eeprom_info` implementation
 - api: add missing thermal condition and info
 - api: fix return value of `ChassisBase.set_status_led`
 - sfp: introduce SfpOptoeBase implementation used based on configuration knob
 - psu: rely on pmbus to read input/output status when other mechanism is missing
 - misc: other refactors and improvements
2021-09-01 01:52:57 -07:00
Ying Xie
7735e8a792
[7050] define hwsku.json for Arista-7050QX-32S-S4Q31 to skip SFP checks for first 4 ports (#8624)
Why I did it
The first 4 ports on this dut are breakout ports. They might not always be connected in lab. Mark them as 'RJ45' to skip the SFP check since they are by default disabled.

How to verify it
run platform test_reboot.py

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2021-08-31 17:15:03 -07:00
Song Yuan
d53c6248e4
[chassis] Set LAG Id range for 7800 chassis (#8052)
Configure LAG Id range in chassisdb.conf for 7800 chassis.
2021-08-30 16:04:07 -07:00
byu343
85a671f5af
[arista] Add gearbox configs for Arista 7280cr3mk (#8146)
* Add gearbox support for 7280cr3mk and its variants
2021-08-26 15:30:11 +08:00
Samuel Angebault
18cd32a218
[Arista] Add VOQ information for Clearwater2 (#8508)
This change introduces 3 columns in the port_config.ini file.
These are coreId, corePortId and numVoq.
The ports for inband and recirc were also renamed properly.
2021-08-20 16:42:56 -07:00
zzhiyuan
144851fea8
[Arista] Add dynamic port breakout hwsku to platforms (#7975)
Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
Why I did it
To support dynamic port breakout Broadcom configurations on Arista platforms.

How I did it
Updated platform.json for platforms and added new hwsku, Broadcom config, and hwsku.json for dynamic port breakout usage.

The name of the new hwsku name used is very similar to the platform name (platform x86_64-arista_7050_qx32s hwsku Arista-7050QX-32S) as the flex hwsku is meant to be the default in the future.

How to verify it
Boot up device with the new hwsku, interfaces are up.
Change hwsku.json with new default breakout mode and reload device, breakout will have successfully been applied.
2021-08-16 07:03:50 -07:00
gechiang
8e903f4566
BRCM Disable ACL Drop counted towards interface RX_DRP counters (#8382)
* BRCM Disable ACL Drop counted towards interface RX_DRP counters
2021-08-10 19:03:22 -07:00
Neetha John
9acf0744a1
Revert "Revert "Update default cable len to 0m for TD2"" (#8354)
* Update default cable len to 0m for TD2 (#8298)
* Update sonic-cfggen tests with the correct cable len

Signed-off-by: Neetha John <nejo@microsoft.com>

As part of the buffer reclamation efforts for TD2, setting the default cable len to 0m which means unused ports will have a cable len of 0m.

Why I did it
To align with the changes in Azure/sonic-swss#1830

How to verify it
- With the default cable len set to 0m and the associated changes in swss, CABLE_LENGTH table had '0m' set for unused ports and accordingly more space was reserved for the shared pool
- Cfggen tests passed with the cable len update
2021-08-06 10:36:10 -07:00
Neetha John
4268662486
Revert "Update default cable len to 0m for TD2 (#8298)" (#8320)
This reverts commit 93e939b8af.
2021-08-03 14:07:41 -07:00
Neetha John
93e939b8af
Update default cable len to 0m for TD2 (#8298)
Signed-off-by: Neetha John <nejo@microsoft.com>

As part of the buffer reclamation efforts for TD2, setting the default cable len to 0m which means unused ports will have a cable len of 0m.

Why I did it
To align with the changes in Azure/sonic-swss#1830

How to verify it
With the default cable len set to 0m and the associated changes in swss, CABLE_LENGTH table had '0m' set for unused ports and accordingly more space was reserved for the shared pool
2021-08-02 09:09:22 -07:00
Samuel Angebault
6ae5e1d6a1
[Arista] Update platform library submodules (#8281)
- Improve chassis linecard restartability
- Fix 'show system-health' cli by adding non standard api
- Fix ledd crash on linecards with Recycle/Inband ports
- Refactor DPM management and add ADM1266 support
- Add state machine to update DPM RTC clock periodically
- Improve xcvr temperature reporting
- Fix lane mapping and `default_sku` for `x86_64-arista_7170_32c` platform
- Fix `7170-32C/CD` platform definition
2021-07-30 17:10:45 -07:00
Samuel Angebault
545c69180f
[Arista] Improve 7280CR3 platform configurations (#8234)
Introduce Arista-7280CR3-C32P4 and Arista-7280CR3-C32D4 hwskus.
Remove deprecated fancontrol configurations.
Add pcie.yaml configurations
Add missing default_sku files
2021-07-24 13:42:27 -07:00
vmittal-msft
e7cec0928b
Updated SONIC buffer pool settings to accomodate SAI adjustment for Arista-7050CX3-32S-C32 (#8159) 2021-07-16 12:32:16 -07:00
Samuel Angebault
17f0217f30
[Arista] Chassis device configurations (#7529)
Add configurations for the following chassis elements

Fabrics 7804R3-FM, 7808R3-FM and 7808R3A-FM
Linecard 7800R3-48CQ2
Supervisor 7800-SUP*
2021-06-30 18:16:20 -07:00
gechiang
6fc279b7c1
Add BRCM SOC Property to not count ACL drops towards interface RX_DRP… (#7945)
* Add BRCM SOC Property to not count ACL drops towards interface RX_DRP counter for 7050CX3 and 7260CX3 DualToR platforms
2021-06-23 18:09:47 -07:00
judyjoseph
3ad830eb49
New sonic-buildimage images for Broadcom DNX ASIC family. (#7598)
Introduce new sonic-buildimage images for Broadcom DNX ASIC family.

sonic-broadcom-dnx.bin
sonic-aboot-broadcom-dnx.swi

How I did it

NO CHANGE to existing make commands

make init; make configure PLATFORM=broadcom;  make target/sonic-aboot-broadcom.swi; make  target/sonic-broadcom.bin

The difference now is that it will result in new broadcom images for DNX asic family as well. 

sonic-broadcom.bin, sonic-broadcom-dnx.bin
sonic-aboot-broadcom.swi, sonic-aboot-broadcom-dnx.swi

Note: This PR also adds support for Broadcom SAI 5.0 (based on 1.8 SAI ) for DNX based platform + changes in platform x86_64-arista_7280cr3_32p4 bcm config files and platform_env.conf files
2021-06-22 11:12:22 -07:00
abdosi
9f4359804e
Updated 7260 64x100 MMU Profile. (#7849)
What I did:

Updated 7260 MMU Profile based on latest MSFT Tier 1 Tomahawk2_MMU_Setting_48x100G_40m_16x100G_300m_v1.0 and
TH2_PGHdrm_MSFT.

How I verify:
Made sure image is up/traffic is flowing/mmu dump looked fine.
SAI qos test need will be updated to support this SKU.
2021-06-15 22:06:48 -07:00
Andriy Kokhan
12a04704ad
[Arista] Added pcie.yaml for x86_64-arista_7170_32cd (#7788)
Process pcied failed on Arista-7170-32CD-C32
```
root@sonic:/# supervisorctl 
chassis_db_init                  EXITED    Jun 03 08:48 AM
dependent-startup                EXITED    Jun 03 08:48 AM
ledd                             RUNNING   pid 28, uptime 3:07:49
lm-sensors                       EXITED    Jun 03 08:48 AM
pcied                            FATAL     Exited too quickly (process log may have details)
```

Signed-off-by: Andriy Kokhan <andriyx.kokhan@intel.com>
2021-06-09 22:08:47 -07:00
Ying Xie
b2a2cf0750
[7050] updating 7050 MMU configurations (#7801)
Why I did it
7050 S4Q31 mmu configuration is missing ALPM configurations, causing not enough memory reserved for routes. Orchagent crashes on a nightly testbed with 6400 route entries.

How I did it
Add the missing ALPM configurations.

How to verify it
Load the configuration on testbed and verified new configuration exists and no more crash.

Signed-off-by: Ying Xie ying.xie@microsoft.com
2021-06-05 21:50:01 -07:00
Neetha John
239a1cc1df
Rename AristaQX-32S skus (#7751)
This PR contains the following changes
Original Arista-7050-QX-32S sku (32x40G ports) has been renamed to Arista-7050QX32S-Q32
Arista-7050-QX-32S is symlinked to Arista-7050QX-32S-S4Q31 (4x10G, 31x40G ports)

Signed-off-by: Neetha John <nejo@microsoft.com>
2021-05-28 22:46:49 -07:00
Ying Xie
a42aa3d316
[MMU] define T1 MMU configuratino for Arista-7260CX3-Q64 (#7718)
Why I did it
Arista-7260CX3-Q64 is missing T1 MMU configuration.

How I did it
Define T1 MMU configuration for Arista-7260CX3-Q64.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2021-05-27 08:20:07 -07:00
Neetha John
6f884b7278
Update PG profile settings for Arista-7050QX-32S-S4Q31 (#7673)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
PG profile settings need to be aligned with Arista-7050-QX-32S

How I did it
Copy over the current settings from Arista-7050-QX-32S and define params for 10G and 1G speeds as well
2021-05-24 17:15:37 -07:00
Neetha John
f744f9354c
Update MMU and QOS settings for Arista-7050QX-32S-S4Q31 (#7672)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
Need proper MMU and Qos settings for Arista-7050QX-32S-S4Q31

How I did it
Updated the settings based on Arista-7050-QX-32S
2021-05-24 09:33:33 -07:00
vmittal-msft
aae315faaf
Updated MMU settings for Arista-7050CX3-32S-C32 T1 topology (#7597) 2021-05-12 21:28:19 -07:00
Samuel Angebault
e7c26fb0c9
[Arista] Update platform configurations and library (#7527)
Platform library changes
 - Fix the use of /proc/modules during testing, fixes #7463
 - Add `libsfp-eeprom.so` build to read/write xcvr eeproms in C
 - Add some more reboot-cause information
 - Write down temperature hw thresholds to the sensors
 - Report software thresholds through platform api
 - Writ `port_name sysfs` file of optoe`
 - Tests enhancements
 - Fix dependency issues for chassis provisioning

Platform configuration changes
 - Add `pcie.yaml` configuration for a few platforms
 - Mount `libsfp-eeprom.so` inside `pmon`
 - Fix `Arista-7050SX3-48C8` and `Arista-7050SX3-48YC8' platform and hwsku
 - Miscellaneous fixes

Co-authored-by: Boyang Yu <byu@arista.com>
Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2021-05-06 10:59:22 -07:00
vmittal-msft
68dfa704b3
Updated Qos/MMU settings for Arista-7050CX3-32S-C32 & Arista-7050CX3-32S-D48C8 (#7068)
* TD3 Qos/MMU settings for Arista-7050CX3-32S-C32 & Arista-7050CX3-32S-D48C8
2021-04-30 10:02:08 -07:00
zzhiyuan
5f435f2296
[Arista] Add DPB for 7060CX-32S (#7413)
#### Why I did it
- To start support of dynamic port breakout as the norm for Arista platforms.
- Add a DPB hwsku for the 7060CX-32S

#### How I did it
- Expand platform.json for the 7060CX-32S
- Added a new hwsku specifically for DPB
- Added a flex Broadcom configuration

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2021-04-27 11:03:20 -07:00
Christian Svensson
186e1b9b57
[arista] Add DPB for Arista 7050 QX32 (#7342)
This change introduces dynamic port breakout (DPB) for Arista 7050 QX32 model by adding a new SKU suffixed with `-Flex`.

The breakout configuration allowed is the same as in mainline Arista EOS, i.e. 24 first ports are allowed to be used in 4x10G in addition to the default 40G mode. The last 8 ports are fixed to 40G. This is due to ASIC limitations of a total of 104 max ports.

**NOTE**: As described in https://github.com/aristanetworks/sonic/issues/30#issuecomment-820584113 front panel LEDs are likely not working when operating in breakout mode. It is not clear if the LEDs work correctly in 40G mode as I have not had a chance to physically inspect the switch with this patch.

Signed-off-by: Christian Svensson <blue@cmd.nu>
2021-04-27 10:57:07 -07:00
Prince Sunny
dd4d2a75f0
[Broadcom] Set hierarchical ecmp levels to 2 (#7370)
Set hierarchical ecmp level to 2 instead of 3. Based on CS00011833367, ecmp level must be set to 2.
This is already handled for TH2 platforms. Change is required only for TD3

Co-authored-by: Ubuntu <prsunny@prince-vm.vzw1i4tqyeburcdz5lrgulxi2c.yx.internal.cloudapp.net>
2021-04-21 13:22:52 -07:00
gechiang
6f65b42e4c
7260cx3 DualToR config.bcm support based on DualToR setting in device metadata at boot time (#7168)
* 7260cx3 DualToR config.bcm support based on DualToR setting in device metadata at boot time. 
For HWSKU Arista-7260CX3-C64 the MMU setting SOC for T0/T1 is also combined into the config.bcm.j2 logic so use just one config file and adding delta based on Switch Roles.
2021-03-31 14:23:24 -07:00
Dmytro Shevchuk
d8627e6414
[yang] update yang model, add autoneg to sonic-port (#5963)
Dynamic Port Breakout fall in case "autoneg" field exist in config_db.

- How I did it
Added "autoneg" field in sonic-port yang model.

- How to verify it
Add "autoneg" field into config_db like this:

"Ethernet8": {
    "index": "2", 
    "lanes": "8,9,10,11", 
    "fec": "rs", 
    "pfc_asym": "off", 
    "mtu": "9100", 
    "alias": "Ethernet8", 
    "admin_status": "up", 
    "autoneg": "on", 
    "speed": "100000",
},
2021-03-30 08:27:58 -07:00
Ying Xie
832e63554a
[Arista] add MMU configuration for Arista 7260 C64 (#7027)
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2021-03-26 11:10:19 -07:00
Samuel Angebault
178688b415
[Arista] Refresh device folder for DCS-7060DX4-32 (#6942)
As booting on DCS-7060DX4-32 would use the default sku of DCS-7060PX4-32 which is not compatible, 
thus move some files around to properly separate the configurations that are device specific.

Signed-off-by: Samuel Angebault <staphylo@arista.com>
2021-03-05 11:23:47 -08:00
Sujin Kang
d5238ae8dd
[pcie.yaml] Move pcie configuration file path to platform directory (#6475)
- Why I did it
The pcie configuration file location is under plugin directory not under platform directory.
#6437

- How I did it

Move all pcie.yaml configuration file from plugin to platform directory.
Remove unnecessary timer to start pcie-check.service
Move pcie-check.service to sonic-host-services
- How to verify it
Verify on the device
2021-02-21 08:27:37 -08:00
Samuel Angebault
5fb374b03d
[Arista] Driver and platform update (#6468)
- Add support for `DCS-7050SX3-48YC8` and `DCS-7050SX3-48C8` platform
 - Add support for more variants of `DCS-7280CR3-32[PD]4`
 - Add Supervisor to Linecard consutil support
 - Complete Watchdog platform API support
 - Fix some PSU behavior on `DCS-7050QX-32` and `DCS-7060CX-32S`
 - Fix SEU management on `DCS-7060CX-32S`
 - Allow kernel modules to build up to linux 5.10
 - Rename led color `orange` to `amber`
 - Miscellaneous fixes
2021-02-19 10:48:52 -08:00
vmittal-msft
02cc486511
Remove dummy MMU profiles for Arista-7050CX3-32S-C32 and Arista-7050CX3-32S-D48C8 (#6785) 2021-02-17 11:45:00 -08:00
Vaibhav Hemant Dixit
a7ba1b8b43
Add the 10G ports with updated speed (#6699)
Port_config update for hwsku 7050CX3-32S-C3 - add two 10G ports.
This change is added to fix issue of "PortsOrch initialization failure" seen by previous removal of these 10G ports.
Tested on the device with new minigraph, and the PortsOrch initialization failure is not seen.
2021-02-05 19:34:17 -08:00
gechiang
c98e8d6690
[BCM Config] Update TD3 bcm.config files to use ISSU capable premium CANCUN 6.4.1 (#6651) 2021-02-02 21:48:26 -08:00
Vaibhav Hemant Dixit
580666a406
[arista]: 7050CX3-32S-C32: Remove unused 10G ports and update speed (#6638)
port_config.ini for HWSKU Arista-7050CX3-32S-C32 has missing speed column and duplicated lanes.
The incorrect speed causes issues in Orchagent RESTARTCHECK as the below task remains as the remaining item during swss shutdown.
2021-02-02 11:26:36 -08:00
Tamer Ahmed
284c2738e8
[sonic-device-data]: Update BRCM Tunnel/ECMP Parameter For 7050cx3 SKUs (#6415)
Update Tunnel and ECMP parameters for brcm 7050cx3 48x50G+8x100G and 32x100G SKUs.

signed-off-by: Tamer Ahmed <tamer.ahmed@microsoft.com>
2021-01-29 14:15:48 -08:00
Samuel Angebault
4e0a869b44
[arista]: Add placeholder healthd configuration for all platforms (#6233)
Prevent system-healthd from service from failing at boot time due to missing configuration.
Also adds basic support for healthd.
The following caveat exists with this placeholder configuration:
 - No PSU monitoring (sensors/fans)
 - No ASIC temperature monitoring
2020-12-17 05:18:38 -08:00
zzhiyuan
4d4b489a5f
Add platform.json to Arista platforms (#6150)
platform.json is needed for sonic-mgmt testing. Also in the future it will be used as part of dynamic port breakout.

Also removed the folder symlink for BlackhawkDD because it has a different platform.json than BlackhawkO.

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2020-12-08 10:20:13 -08:00
Samuel Angebault
468aac92b7
[Arista] Update platform configurations for 7060DX4 and 7060PX4 (#6084)
Current support for the 7060PX4-32 and 7060DX4 was broken.
With this change, ports are now linking fine.

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2020-12-04 10:11:06 -08:00
Nazar Tkachuk
be145b613c
[Arista] Rename chip in sensors.conf for 7170 platform (#6026)
Rename chip name dps1900-i2c-X-58 to pmbus-i2c-X-58 in sensors.conf for Arista 7170 due to latest updates for Arista driver submodules #5686. After these updates adapter dps1900 was renamed and sensors.conf file is not applied properly. Issue was observed started from BFN SONiC image 16.

Signed-off-by: Nazar Tkachuk <nazarx.tkachuk@intel.com>
2020-12-01 15:57:31 -08:00
Joe LeVeque
7f4ab8fbd8
[sonic-utilities] Update submodule; Build and install as a Python 3 wheel (#5926)
Submodule updates include the following commits:

* src/sonic-utilities 9dc58ea...f9eb739 (18):
  > Remove unnecessary calls to str.encode() now that the package is Python 3; Fix deprecation warning (#1260)
  > [generate_dump] Ignoring file/directory not found Errors (#1201)
  > Fixed porstat rate and util issues (#1140)
  > fix error: interface counters is mismatch after warm-reboot (#1099)
  > Remove unnecessary calls to str.decode() now that the package is Python 3 (#1255)
  > [acl-loader] Make list sorting compliant with Python 3 (#1257)
  > Replace hard-coded fast-reboot with variable. And some typo corrections (#1254)
  > [configlet][portconfig] Remove calls to dict.has_key() which is not available in Python 3 (#1247)
  > Remove unnecessary conversions to list() and calls to dict.keys() (#1243)
  > Clean up LGTM alerts (#1239)
  > Add 'requests' as install dependency in setup.py (#1240)
  > Convert to Python 3 (#1128)
  > Fix mock SonicV2Connector in python3: use decode_responses mode so caller code will be the same as python2 (#1238)
  > [tests] Do not trim from PATH if we did not append to it; Clean up/fix shebangs in scripts (#1233)
  > Updates to bgp config and show commands with BGP_INTERNAL_NEIGHBOR table (#1224)
  > [cli]: NAT show commands newline issue after migrated to Python3 (#1204)
  > [doc]: Update Command-Reference.md (#1231)
  > Added 'import sys' in feature.py file (#1232)

* src/sonic-py-swsssdk 9d9f0c6...1664be9 (2):
  > Fix: no need to decode() after redis client scan, so it will work for both python2 and python3 (#96)
  > FieldValueMap `contains`(`in`)  will also work when migrated to libswsscommon(C++ with SWIG wrapper) (#94)

- Also fix Python 3-related issues:
    - Use integer (floor) division in config_samples.py (sonic-config-engine)
    - Replace print statement with print function in eeprom.py plugin for x86_64-kvm_x86_64-r0 platform
    - Update all platform plugins to be compatible with both Python 2 and Python 3
    - Remove shebangs from plugins files which are not intended to be executable
    - Replace tabs with spaces in Python plugin files and fix alignment, because Python 3 is more strict
    - Remove trailing whitespace from plugins files
2020-11-25 10:28:36 -08:00
Ying Xie
1ba583cb46
[TD3] add dummy MMU configuration for Arista-7050CX3-32S-D48C8 (#5950)
Need A mmu configuration to get the device going without generating lots of warnings.

Similar to dummy MMU configuration for Arista-7050CX3-32S-C32, this configuration will need to be updated with correct numbers. This MMU configuration is copied from 7060 comparable hwsku.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2020-11-17 19:01:39 -08:00
Lawrence Lee
d0f16c0d79
Make backend device checking more robust (#5730)
Treat devices that are ToRRouters (ToRRouters and BackEndToRRouters) the same when rendering templates
 Except for BackEndToRRouters belonging to a storage cluster, since these devices have extra sub-interfaces created
Treat devices that are LeafRouters (LeafRouters and BackEndLeafRouters) the same when rendering templates

Signed-off-by: Lawrence Lee <lawlee@microsoft.com>
2020-11-10 15:06:35 -08:00
Ying Xie
6a8ebef449
[Arista 7050cx3] add dummy MMU configurations for Arista-7050CX3-32S-C32 (#5798)
- Why I did it
On Arista-7050CX3-32S-C32, there are constant stream of errors like following.

Nov 3 21:56:24.415190 str2-7050cx3-acs-06 NOTICE swss#orchagent: :- registerInWdDb: No lossless TC found on port Ethernet68

Which causes:

loganalyzer to claim test failed.
leaving the system without MMU configuration. Which couldn't be good for any IO test.
- How I did it
Added these MMU configuraions are copied from another platform and guaranteed to be incorrect for hwsku Arista-7050CX3-32S-C32.

Adding them so that we have A MMU configuration and the system won't throw a whole bunch of errors and leave MMU unconfigured. The correct MMU configuration will come later.

This configuration is definitely not suitable for testing system performance or QoS behavior.

Signed-off-by: Ying Xie ying.xie@microsoft.com

- How to verify it
Test will have chance to pass. Ran a few test that would fail otherwise.
2020-11-09 13:27:36 -08:00
Baptiste Covolato
527a69dfbf
[arista/7800r3_48cq(m)2_lc] remove platform_reboot (#5653)
We don't need a custom platform reboot on Clearwater2(Ms). They are expected to be rebooted via a normal linux soft reboot.

Remove symlink to the arista common platform reboot for those 2 platforms.
2020-10-29 16:26:41 -07:00
Samuel Angebault
5bfe37ca42
[Arista] Update driver submodules (#5686)
- Enable thermalctld support for our platforms
 - Fix Chassis.get_num_sfp which had an off by one
 - Implement read_eeprom and write_eeprom in SfpBase
 - Refactor of Psus and PsuSlots. Psus they are now detected and metadata reported
 - Improvements to modular support

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2020-10-23 12:28:36 -07:00
BrynXu
a2e3d2fcea
[ChassisDB]: bring up ChassisDB service (#5283)
bring up chassisdb service on sonic switch according to the design in
Distributed Forwarding in VoQ Arch HLD

Signed-off-by: Honggang Xu <hxu@arista.com>

**- Why I did it**
To bring up new ChassisDB service in sonic as designed in ['Distributed forwarding in a VOQ architecture HLD' ](90c1289eaf/doc/chassis/architecture.md). 

**- How I did it**
Implement the section 2.3.1 Global DB Organization of the VOQ architecture HLD.

**- How to verify it**
ChassisDB service won't start without chassisdb.conf file on the existing platforms.
ChassisDB service is accessible with global.conf file in the distributed arichitecture.

Signed-off-by: Honggang Xu <hxu@arista.com>
2020-10-14 15:15:24 -07:00
zzhiyuan
3da996bbf8
[arista]: Add disable_pcie_firmware_check soc property (#5543)
This is to fix pcie firmware check assert in Broadcom SDK once the SAI changes merges. This will be in the future but adding the soc property in the broadcom config now.

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2020-10-06 18:35:15 -07:00
Samuel Angebault
a24b581d80
[Arista] Add pcie.yaml configuration file for a few platforms (#5527)
* Add pcie.yaml configuration for Gardena
* Add pcie.yaml configuration for Upperlake
* Add pcie.yaml configuration for Clearlake
* Add pcie.yaml configuration for Lodoga
2020-10-02 09:05:43 -07:00
Samuel Angebault
4ec83b25bc
[arista]: Add new 48x50G + 8x100G hwsku for Lodoga (#5452) 2020-09-23 22:41:07 -07:00
abdosi
a6a10f05b7
In SAI 3.5 by default we are supporting 256 Group with 64 Memeber each. (#5400)
However in SAI 3.7 default behaviout got changes to 128 Group and 128
    Memeber each.

    This change is to make sure we are using same ECMP Group/Memeber Per
    Group for 3.7 also so that behaviour is consistent.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2020-09-22 11:21:12 -07:00
Samuel Angebault
0b4191fe2a
[Arista] Updating driver submodules (#5352)
- Merge chassis codebase upstream
 - Add support for Otterlake supervisor
 - Add support for NorthFace and Camp chassis
 - Add support for Eldridge, Dragonfly and Brooks fabrics
 - Add support for Clearwater2 and Clearwater2Ms linecards
 - Add new arista Cli to power on/off cards
 - Add new arista show Cli to inspect supervisor, chassis, fabrics and linecards
2020-09-10 01:34:38 -07:00
Wei Bai
0b6fd70767
Update PG profiles for Arista 7050 (#5324)
* Update pg_profile_lookup.ini
2020-09-08 11:57:21 -07:00
abdosi
b6efb49817
Update bcm soc property bcm_num_cos from 8 to 10 (#5314)
as needed by SAI 3.7 and above. Without this change
Warmboot fails from 3.5 to 3.7 as Braodcoam Datastructure
gets corrupted after warm-boot.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2020-09-04 07:40:17 -07:00
zzhiyuan
2c426a8290 Skip thermalctld for arista platforms (#4893)
thermalctld throwing error messages because it is not yet fully configured, disabling it for now on arista platforms.

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2020-07-12 18:08:51 +00:00
Samuel Angebault
c8bd640ae5
[arista] Update drivers submodules (#4693)
- Sensor and Fan information added to primary platforms for thermal API.
- Refactors involving better abstractions, code reuse and dead code removal.
- Improvements to the diag capabilities
- Pylintrc added to improve code quality. Will become fatal at a later time.

Co-authored-by: Baptiste Covolato <baptiste@arista.com>
2020-06-04 13:33:33 -07:00
Samuel Angebault
d35a8a3800
[arista]: Add SmartsvilleDDBK and SmartsvilleBkMs (#4662)
Co-authored-by: Boyang Yu <byu@arista.com>
2020-05-28 14:59:00 -07:00
Samuel Angebault
de4fa1874a
[arista]: remove the soc property disabling sram scan (#4623) 2020-05-20 12:44:48 -07:00
Neetha John
286aa35ac6
[qos]: Alpha and ECN settings change for Th (#4564)
Dynamic threshold setting changed to 0 and WRED profile green min threshold set to 250000 for Tomahawk devices

Changed the dynamic threshold settings in pg_profile_lookup.ini
Added a macro for WRED profiles in qos.json.j2 for Tomahawk devices
Necessary changes made in qos.config.j2 to use the macro if present

Signed-off-by: Neetha John <nejo@microsoft.com>
2020-05-09 11:21:18 -07:00
Samuel Angebault
5b0ec7afe6
[Arista] Update drivers submodules (#4317)
* Update arista drivers submodules

* Add device configs for 7060CX2-32S

* Update boot0 and union-mount for 7060CX2-32S

* Add 7170-32C and 7170-32CD support in boot0

* Sync after writting boot configs

* Add 7170-32C and 7170-32CD device configurations

Co-authored-by: Boyang Yu <byu@arista.com>
2020-03-27 17:28:27 -07:00
byu343
ae52223892
[arista]: Add fancontrol for arista 7050cx3 (#4121) 2020-02-11 13:19:07 -08:00
Samuel Angebault
64500e143b [Arista] Update drivers and boot script (#3959)
* Update arista driver submodule

* Add support for 7260CX3-64E in boot0

* Refactor boot0 platform specific definition

Make it easier to manage new sku

* Add support for 7050CX3-32S in boot0

Just contains the required boot0 information

* Add basic plugin support for DCS-7050CX3-32S

* Add port config for Arista-7050CX3-32S-C32

Co-authored-by: yurypm <yurypm@arista.com>
Co-authored-by: byu343 <byu@arista.com>
2020-01-17 10:44:49 -08:00
byu343
8a7c1300c2 [devices]: Fix the clock setting on arista 7280 (#3788)
* Fix serdes setting for B0/B1 revision chip on 7280
2019-11-21 16:21:08 -08:00
Andriy Kokhan
fc495dc10e [barefoot][build] Fixed BFN platform build failure (#3766)
Signed-off-by: Andriy Kokhan <akokhan@barefootnetworks.com>
2019-11-19 22:14:29 -08:00
Samuel Angebault
05e659901f [arista] Add support for more 7280CR3 variants (#3711)
* Add extra Smartsville hwskus
2019-11-06 10:11:38 -08:00
zzhiyuan
4026a8bc8d Remove macro generate_pg_profils for 7170 buffer (#3635) 2019-10-24 16:48:46 -07:00
Wenda Ni
0d2aa7fb5b [devices]: PG headroom change for Arista 7260 (#3600)
Signed-off-by: Wenda Ni <wenni@microsoft.com>
2019-10-15 06:03:48 -07:00
byu343
28c358b491 Add hwSku Arista-7280CR3-C28S8 (#3574) 2019-10-08 12:05:24 -07:00
zzhiyuan
f3cfa8fdff Fix buffer configurations for 7170 (#2972)
* Fix buffer configurations for 7170

* Adjust buffer configurations for 7170

* Remove ingress lossless profiles for Arista 7170
2019-10-04 10:14:09 -07:00
Ying Xie
eeeda28434
[bcm config] enable sram scan (#3558)
Per Broadcom's recommendations.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2019-10-03 17:02:59 -07:00
Wenda Ni
7b0a5ba6ae Remove the divide by 4 operation to the under the hood SAI (#1532)
* Remove the divide by 4 operation to the under the hood SAI

This is to avoid the need and thus the confusion for application program to know
the mmu internal architecture

This change must have support from SAI change to reach the correct
config

Signed-off-by: Wenda <wenni@microsoft.com>

* Relegate the divide by 4 operation to the under the hood SAI for egress
lossless pool

Extend to 7060 and 6100

Signed-off-by: Wenda <wenni@microsoft.com>

* Add more TH/TH2 hwskus

Signed-off-by: Wenda Ni <wenni@microsoft.com>

* Update config test

Signed-off-by: Wenda Ni <wenni@microsoft.com>

* Add TH2 ingress lossy profile

Signed-off-by: Wenda Ni <wenni@microsoft.com>

* Move the divide by 4 operation to SAI internal

Signed-off-by: Wenda Ni <wenni@microsoft.com>

* [bcm SAI] Upgrade Broadcom SAI to version 3.5.3.1-15

- Broadcom SAI 3.5 GA release 20190924.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2019-09-25 15:57:07 -07:00
byu343
2f63e90b8b [device/arista] Add hwSku Arista-7280CR3-C40 for 7280 (#3477)
* Add hwSku Arista-7280CR3-C40

* Clean empty lines

* Fix violation to config_checker

* Fix no new line at end
2019-09-23 18:07:20 -07:00
zzhiyuan
1840bef1a1 [devices]: Add serdes tuning for Arista 7060PX4 32x400G (#3382) 2019-08-28 08:44:13 -07:00
Andriy Kokhan
f468bc7859 [barefoot]: updated SDK to 9.0 pre-release (#3350)
Signed-off-by: Andriy Kokhan <akokhan@barefootnetworks.com>
2019-08-19 10:28:00 -07:00
Ying Xie
99b0b349bf
[mmu] add mmu_init_config to HWSKU Arista-7260CX3-Q64 (#3334)
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2019-08-13 17:31:25 -07:00
zzhiyuan
0ef7dc5d98 [devices]: Update Arista 7260CX3-64 10G SFP tuning (#3151) 2019-07-16 08:42:55 -07:00
zzhiyuan
16e85712b7 [devices]: Add tuning for Arista 7060PX/DX4 32x400G (#3145)
* Add serdes polarity for 32x400G Arista 7060PX/DX4

* Add serdes polarity for 64x100G on Arista 7060PX/DX4
2019-07-12 11:25:19 -07:00
Wenda Ni
dbdc166f6f
Add new hwsku Arista-7050QX32S-Q32 (#3091)
Signed-off-by: Wenda Ni <wenni@microsoft.com>
2019-06-27 17:22:44 -07:00
Andriy Kokhan
4f35cce27b [bfn] added TNA config for all devices (#3029)
Signed-off-by: Andriy Kokhan <akokhan@barefootnetworks.com>
2019-06-22 14:50:14 -07:00
Samuel Angebault
df063bd78d [device/Arista] Add initial support for platform API (#2964)
* Congregate plugin scripts for Arista platforms

* Update arista driver submodules

Pulls new platform API related changes
2019-06-07 09:01:09 -07:00
Samuel Angebault
d84aa49d38 [device/Arista] Add HwSku profiles for the 7060PX-32 (#2973)
* Add port configuration for HWSKU Arista-7060PX4-O32

* Add 64x100G configuration for 7060PX4-32
2019-06-06 15:38:11 -07:00
Samuel Angebault
aac0c24312 [device/Arista] Add support for the 7280CR3-32P4 (#2910)
* Add boot0 support for the 7280CR3

* Add platform and plugins for 7280CR3

* Add port config for 7280CR3

* Add platform_reboot for 7280CR3

* Add support for 7280CR3-32D4 based on the 7280CR3-32P4

* Update arista driver submodules

 - Introduce new 7280CR3-32P4
 - Improve to the led plugin for OSFP
2019-05-18 10:34:07 -07:00
Samuel Angebault
77cde50541 [device/Arista] Improvements to the boot of Arista devices. (#2898)
* Fix showing systemd shutdown sequence when verbose is set

* Fix creation of kernel-cmdline file

Sometimes boot0 prints error
"mv: can't preserve ownership of '/mnt/flash/image-arsonic.xxxx/kernel-cmdline': Operation not permitted"

* Improve flash space usage during installation

Some older systems only have 2GB of flash available. Installing a second
image on these can prove to be challenging.
The new installation process moves the installer swi to memory in order
to avoid free up space from the flash before uncompressing it there.
It removes all the flash space usage spike and also improves the IO
since the installation is no more reading and writting to the flash at
the same time.

* Add support of 7060CX-32S-SSD

* 7260CX3: use inventory powerCycle procedures

* 7050QX-32S: use inventory powerCycle procedures

* 7050QX-32: use inventory powerCycle procedures

* platform: arista: add common platform_reboot

Replace platform_reboot by a link to new common for devices already
using a similar script.

* 7060CX-32S: use inventory powerCycle procedures

* Install python smbus in pmon

Some platform plugin need the python smbus library to perform some actions.
This installs the dependency.
2019-05-15 12:45:05 -07:00
zzhiyuan
b7235fc949 [Arista] Add QoS needed files for Arista 7170 (#2814) 2019-05-09 00:25:09 -07:00
Michel Moriniaux
62e994d8ec [HWSKU] add Arista-7060CX-32S-T96C8 and Arista-7060CX-32S-Q24C8 (#2617)
* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU

Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>

* [HWSKU] Added Arista-7060CX-32S-T96C8 HWSKU

Added the bcm config files for a 96x25G+8x100G ToR

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>

* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU

Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
2019-03-15 09:45:17 -07:00
zzhiyuan
4361c2d758 [devices]: Add autoneg to 7170-Q59S20 (#2636) 2019-03-06 00:18:48 -08:00
zzhiyuan
637e435fd2 [devices]: Fix sfputil indexing for Arista 7170-Q59S20 (#2623) 2019-03-01 12:47:50 -08:00
zzhiyuan
4d863fa032 Fix port_config for 7170-Q59S20 (#2618) 2019-02-28 15:04:04 -08:00
Ying Xie
f98bec41c7
[HWSKU] Define HWSKU Arista-7260CX3-Q64 and Arista-7260CX3-Q44 (#2562)
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2019-02-14 11:27:15 -08:00
zzhiyuan
6037707abc [devices]: Add device data for Arista 7060PX/DX4-32 (#2534)
* Add boot0 definition for Arista 7060PX4-32 and 7060DX4-32

* Add port configuration for Arista 7060PX4-32

* Add plugins for Arista 7060PX4-32

* Add platform_reboot for Arista 7060PX4-32

* Add Arista 7060DX4-32 as symlink of 7060PX4-32

* Add sensors configuration and fancontrol for Arista 7060PX4-32

* Update arista-driver submodules for barefoot/broadcom

* Add platform_reboot script for Alhambra

* Rook fancontrol CPLD rename
2019-02-08 22:02:01 -08:00
Wenda Ni
1cc6afc9a9 [QoS]: fix size and xoff value on a7050-QX-32S, -QX32, and s6000(#2527)
Signed-off-by: Wenda <wenni@microsoft.com>
2019-02-04 22:27:01 -08:00
Wenda Ni
ce9a3f0c5a [QoS]: QoS Config change for multiple devices (#2505)
* QoS config change: 1) DSCP mapping; 2) link pg/queue 6 to lossy buffer;
3) redistribute scheduler

Signed-off-by: Wenda <wenni@microsoft.com>

* Add scheduling weight to queue 2

Signed-off-by: Wenda <wenni@microsoft.com>

* Link pg/queue 2 to lossy buffer

Signed-off-by: Wenda <wenni@microsoft.com>

* Update the pg headroom for a7060-D48C8 50G

Signed-off-by: Wenda <wenni@microsoft.com>

* Update config gen test for qos

Signed-off-by: Wenda <wenni@microsoft.com>

* Update pg headroom size, and update egress lossy pool size accordingly

Signed-off-by: Wenda <wenni@microsoft.com>

* Update headroom pool size; Update ingress service pool and egress lossy
pool sizes accordingly;

Signed-off-by: Wenda <wenni@microsoft.com>

* a7260: update headroom pool size; Update ingress service pool and egress lossy pool sizes accordingly;

Signed-off-by: Wenda <wenni@microsoft.com>

* Update config gen test for buffer

Signed-off-by: Wenda <wenni@microsoft.com>
2019-01-30 19:00:13 -08:00
zzhiyuan
0256af3f5a Add new hwsku Arista-7170-Q59S20 (#2450) 2019-01-15 23:07:12 -08:00
Wenda Ni
b7330ddfc3 [buffer]: Add buffer defaults for t0 on s6000 and a7050 (#2438)
Signed-off-by: Wenda <wenni@microsoft.com>
2019-01-15 15:34:33 -08:00
Wenda Ni
f5e678cf84 Port QoS & buffer changes in 0330 to master (#2239)
* 1) DSCP 46 to 5; 2) ecn config for lossless traffic; 3) ecn on by default; 4) DWRR equal weight;

Signed-off-by: Wenda <wenni@microsoft.com>

* 1) link pg & queue 5 to lossy buffer profile; 2) ingress lossless alpha 1/8

Signed-off-by: Wenda <wenni@microsoft.com>

* Update the test case for qos & buffer json template

Signed-off-by: Wenda <wenni@microsoft.com>

* Migrate a7050-qx32 and s6000 to use pg_profile lookup architecture

Signed-off-by: Wenda <wenni@microsoft.com>

* Update pg headroom egress service pool for a7050-qx-32s, a7050-qx32, and s6000

Signed-off-by: Wenda <wenni@microsoft.com>

* Link queue 5 to lossy profile

Signed-off-by: Wenda <wenni@microsoft.com>
2018-12-04 20:51:55 -08:00
Samuel Angebault
989b60059b [device/arista]: Update (#2336)
* Update arista drivers submodule

* Ignore the possible timestamp warning in tar extraction

* Add verbosity toggle to boot0

Console logging is slow because of the 9600 baud rate.
Some time can be saved by decreasing the console verbosity.

* Add hook mechanism in boot0.

Support additional features in boot0 via hooks.
Hooks are unpacked and executed at post-install or pre-exec time.

* Fix 7170 sensors.conf file

Fix critical temperature settings for MAX6658 sensors

* Fix the random swap of storage devices

For arista 7050 switches running with linux 4.9, it is likely the device
name of flash drive (/dev/sda) and usb (/dev/sdb) randomly swap in kernel
booting, depending on which one is ready first. It breaks the expectation
that flash will be mounted as root by setting root=/dev/sda1. This patch
will correct ROOT to flash device refering to the path under block_flash.

* Fix 7170 fancontrol

* Do not remove aquota.user file in boot0

This file is a filesystem protected file used by EOS.
It can be simply removed and will make the SONiC installation failed if
not skipped.
2018-12-04 10:08:55 -08:00
Sagar Balani
e5af5d7d1b [barefoot]: change board map json format for arista 7170 (#2234) 2018-11-08 00:21:02 -08:00
zzhiyuan
c904baf579 [devices]: Add index column for 7170 port config (#2195) 2018-10-26 09:06:26 -07:00
Wenda Ni
77652c55fd [QoS]: Unify qos json by using qos_config.j2 template (#2023)
* Unify qos config with qos_config.j2 template

Signed-off-by: Wenda <wenni@microsoft.com>

* Change 7050 to use qos config template

Signed-off-by: Wenda <wenni@microsoft.com>

	modified:   device/arista/x86_64-arista_7050_qx32/Arista-7050-QX32/qos.json.j2
	modified:   device/arista/x86_64-arista_7050_qx32s/Arista-7050-QX-32S/qos.json.j2

* Change a7060, a7260, s6000, s6100, z9100  to use qos config template

Signed-off-by: Wenda <wenni@microsoft.com>

* Change mlnx devices to use qos config template

Signed-off-by: Wenda <wenni@microsoft.com>

	modified:   ../../../mellanox/x86_64-mlnx_msn2100-r0/ACS-MSN2100/qos.json.j2
	modified:   ../../../mellanox/x86_64-mlnx_msn2410-r0/ACS-MSN2410/qos.json.j2
	modified:   ../../../mellanox/x86_64-mlnx_msn2700-r0/ACS-MSN2700/qos.json.j2
	modified:   ../../../mellanox/x86_64-mlnx_msn2700-r0/Mellanox-SN2700-D48C8/qos.json.j2

* Change barefoot devices to use qos config template

Signed-off-by: Wenda <wenni@microsoft.com>

	modified:   barefoot/x86_64-accton_wedge100bf_32x-r0/montara/qos.json.j2
	modified:   barefoot/x86_64-accton_wedge100bf_65x-r0/mavericks/qos.json.j2

* Change accton as7212 to use qos config template

Signed-off-by: Wenda <wenni@microsoft.com>

	modified:   accton/x86_64-accton_as7212_54x-r0/AS7212-54x/qos.json.j2

* Apply PORT_QOS_MAP to active ports only

Signed-off-by: Wenda <wenni@microsoft.com>

* Update qos config test with qos_config.j2 template

Signed-off-by: Wenda <wenni@microsoft.com>

* Update sample output of qos-dell6100.json

Signed-off-by: Wenda <wenni@microsoft.com>

* Remove generating the default port name and index list, i.e., remove the generate_port_lists macro, because PORT is always defined

Signed-off-by: Wenda <wenni@microsoft.com>

* Include pfc_to_pg_map according to platform asic type obtained from
/etc/sonic/sonic_version.yml rather than specifying per hwsku

Signed-off-by: Wenda Ni <wenni@microsoft.com>

* Customize TC_TO_PRIORITY_GROUP_MAP and
PFC_PRIORITY_TO_PRIORITY_GROUP_MAP for barefoot

Signed-off-by: Wenda <wenni@microsoft.com>

* Unify PFC_PRIORITY_TO_PRIORITY_GROUP_MAP: remove "0":"0", "1":"1" as
these two pgs do not generate PFC frames.

Signed-off-by: Wenda <wenni@microsoft.com>
2018-10-17 14:10:34 -07:00
zzhiyuan
3fb150a275 [devices]: Add platform code for 7170 barefoot (#2158) 2018-10-16 00:10:55 -07:00
Ying Xie
5ab66b191a
[bcm config] remove scache_filename config entry (#2140)
Warm boot is managed by SAI. This configuration entry shouldn't be
included in bcm config.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2018-10-12 08:05:38 -07:00
zzhiyuan
7cdf3cb7f7 [devices]: Fix broadcom lane map for 7050-QX32S (#2120)
First port lane map needs to be swapped.
2018-10-04 14:31:54 -07:00
Samuel Angebault
e72d63cf92 [arista] Update Arista drivers submodule (#2097)
* [arista] Update Arista drivers submodule

* Fix 7050qx32 fancontrol for kernel 4.9

* Fix 7060cx32s fancontrol for kernel 4.9

* Install python3-yaml for sonic config tests

* Fix 7260cx3 fancontrol for kernel 4.9

* Fix hwsku-init scripts and permissions

* Preserve old_config folder in boot0
2018-09-28 21:27:41 -07:00
Ying Xie
bd96e097a9 [7050] device specific hwsku-init file needs execution privilege (#2101)
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2018-09-28 14:16:45 -07:00
Ying Xie
11ac4fe76e [7050] Rename HWSKU Arista-7050-Q31S4 to Arista-7050QX-32S-S4Q31 (#2090)
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2018-09-27 01:11:18 -07:00
zzhiyuan
9b2a5943bd [devices]: Add new hwsku Arista-7050-Q31S4 (#2075) 2018-09-25 01:24:31 -07:00
Taoyu Li
018b5899be [updategraph] add support to use preset config instead of default minigraph (#2050)
* [updategraph] add support to use preset config instead of default minigraph

* Fix variable case

* Remove default minigraph case

* Remove default minigraphs and add default_sku files
2018-09-21 22:01:10 -07:00
Ying Xie
e7ef637a09
[config-bcm] move broadcom config files to device folder (#1947)
- Future versions of SAI packages will stop carrying these files.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2018-08-20 10:11:11 -07:00