Updated Qos/MMU settings for Arista-7050CX3-32S-C32 & Arista-7050CX3-32S-D48C8 (#7068)

* TD3 Qos/MMU settings for Arista-7050CX3-32S-C32 & Arista-7050CX3-32S-D48C8
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vmittal-msft 2021-04-30 10:02:08 -07:00 committed by GitHub
parent 3967c28a76
commit 68dfa704b3
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11 changed files with 130 additions and 1 deletions

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@ -0,0 +1,2 @@
{%- set default_topo = 't0' %}
{%- include 'buffers_config.j2' %}

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@ -0,0 +1,46 @@
{%- set default_cable = '300m' %}
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,32) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "32712448",
"type": "ingress",
"mode": "dynamic",
"xoff": "1622016"
},
"egress_lossy_pool": {
"size": "24709632",
"type": "egress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "32599040",
"type": "egress",
"mode": "static"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
"size":"0",
"dynamic_th":"3"
},
"egress_lossless_profile": {
"pool":"[BUFFER_POOL|egress_lossless_pool]",
"size":"0",
"static_th":"32599040"
},
"egress_lossy_profile": {
"pool":"[BUFFER_POOL|egress_lossy_pool]",
"size":"1792",
"dynamic_th":"-1"
}
},
{%- endmacro %}

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@ -0,0 +1,8 @@
# PG lossless profiles.
# speed cable size xon xoff threshold xon_offset
50000 5m 4608 4608 33792 -3 4608
100000 5m 4608 4608 49408 -3 4608
50000 40m 4608 4608 36352 -3 4608
100000 40m 4608 4608 54528 -3 4608
50000 300m 4608 4608 55296 -3 4608
100000 300m 4608 4608 92672 -3 4608

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@ -0,0 +1 @@
{%- include 'qos_config.j2' %}

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@ -48,6 +48,11 @@ robust_hash_disable_vlan=1
stable_size=0x5500000
tdma_timeout_usec=15000000
tslam_timeout_usec=15000000
sai_optimized_mmu=1
mmu_init_config="TD3-MSFT-T0-100G"
buf.map.egress_pool0.ingress_pool=0
buf.map.egress_pool1.ingress_pool=0
buf.map.egress_pool2.ingress_pool=1
phy_chain_rx_lane_map_physical{1.0}=0x1302
phy_chain_rx_lane_map_physical{101.0}=0x0213
phy_chain_rx_lane_map_physical{105.0}=0x2031
@ -509,4 +514,4 @@ serdes_preemphasis_119=0x14410a
serdes_preemphasis_123=0x14410a
serdes_preemphasis_127=0x14410a
serdes_driver_current_130=0xe
serdes_preemphasis_130=0x102804
serdes_preemphasis_130=0x102804

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@ -0,0 +1,2 @@
{%- set default_topo = 't0' %}
{%- include 'buffers_config.j2' %}

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@ -0,0 +1,47 @@
{%- set default_cable = '300m' %}
{%- macro generate_port_lists(PORT_ALL) %}
{# Generate list of ports #}
{%- for port_idx in range(0,32) %}
{%- if PORT_ALL.append("Ethernet%d" % (port_idx * 4)) %}{%- endif %}
{%- endfor %}
{%- endmacro %}
{%- macro generate_buffer_pool_and_profiles() %}
"BUFFER_POOL": {
"ingress_lossless_pool": {
"size": "32669440",
"type": "ingress",
"mode": "dynamic",
"xoff": "2058240"
},
"egress_lossy_pool": {
"size": "24192256",
"type": "egress",
"mode": "dynamic"
},
"egress_lossless_pool": {
"size": "32340992",
"type": "egress",
"mode": "static"
}
},
"BUFFER_PROFILE": {
"ingress_lossy_profile": {
"pool":"[BUFFER_POOL|ingress_lossless_pool]",
"size":"0",
"dynamic_th":"3"
},
"egress_lossless_profile": {
"pool":"[BUFFER_POOL|egress_lossless_pool]",
"size":"0",
"static_th":"32340992"
},
"egress_lossy_profile": {
"pool":"[BUFFER_POOL|egress_lossy_pool]",
"size":"1792",
"dynamic_th":"-1"
}
},
{%- endmacro %}

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@ -0,0 +1,8 @@
# PG lossless profiles.
# speed cable size xon xoff threshold xon_offset
50000 5m 4608 4608 79872 -3 4608
100000 5m 4608 4608 54528 -3 4608
50000 40m 4608 4608 39936 -3 4608
100000 40m 4608 4608 60416 -3 4608
50000 300m 4608 4608 61440 -3 4608
100000 300m 4608 4608 103680 -3 4608

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@ -0,0 +1 @@
{%- include 'qos_config.j2' %}

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@ -48,6 +48,11 @@ robust_hash_disable_vlan=1
stable_size=0x5500000
tdma_timeout_usec=15000000
tslam_timeout_usec=15000000
sai_optimized_mmu=1
mmu_init_config="TD3-MSFT-T0-50G"
buf.map.egress_pool0.ingress_pool=0
buf.map.egress_pool1.ingress_pool=0
buf.map.egress_pool2.ingress_pool=1
phy_chain_rx_lane_map_physical{1.0}=0x1302
phy_chain_rx_lane_map_physical{5.0}=0x3120
phy_chain_rx_lane_map_physical{9.0}=0x3120

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@ -230,3 +230,7 @@ pbmp_gport_stack
reglist_enable
scache_filename
host_as_route_disable
sai_optimized_mmu
buf.map.egress_pool0.ingress_pool
buf.map.egress_pool1.ingress_pool
buf.map.egress_pool2.ingress_pool