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[devices]: Fix the clock setting on arista 7280 (#3788)

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* Fix serdes setting for B0/B1 revision chip on 7280
This commit is contained in:
byu343 2019-11-21 16:21:08 -08:00 committed by Prince Sunny
parent 3470000e3a
commit 8a7c1300c2
3 changed files with 17 additions and 9 deletions
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12
device/arista/x86_64-arista_7280cr3_32p4/Arista-7280CR3-C28S8/jr2-a7280cr3-32p4-28x100G-8x10G.config.bcm
View File

@ -277,11 +277,15 @@ bcm_stat_interval.BCM8869X=1000
mem_cache_enable_ecc.BCM8869X=1
mem_cache_enable_parity.BCM8869X=1
serdes_nif_clk_freq_in.BCM8869X=2
serdes_nif_clk_freq_out.BCM8869X=1
serdes_nif_clk_freq_in.BCM8869X_A0=2
serdes_nif_clk_freq_out.BCM8869X_A0=1
serdes_fabric_clk_freq_in.BCM8869X_A0=2
serdes_fabric_clk_freq_out.BCM8869X_A0=1
serdes_fabric_clk_freq_in.BCM8869X=2
serdes_fabric_clk_freq_out.BCM8869X=1
serdes_nif_clk_freq_in.BCM8869X=1
serdes_nif_clk_freq_out.BCM8869X=bypass
serdes_fabric_clk_freq_in.BCM8869X=1
serdes_fabric_clk_freq_out.BCM8869X=bypass
dram_phy_tune_mode_on_init.BCM8869X=RUN_TUNE

12
device/arista/x86_64-arista_7280cr3_32p4/Arista-7280CR3-C40/jr2-a7280cr3-32p4-40x100G.config.bcm
View File

@ -281,11 +281,15 @@ bcm_stat_interval.BCM8869X=1000
mem_cache_enable_ecc.BCM8869X=1
mem_cache_enable_parity.BCM8869X=1
serdes_nif_clk_freq_in.BCM8869X=2
serdes_nif_clk_freq_out.BCM8869X=1
serdes_nif_clk_freq_in.BCM8869X_A0=2
serdes_nif_clk_freq_out.BCM8869X_A0=1
serdes_fabric_clk_freq_in.BCM8869X_A0=2
serdes_fabric_clk_freq_out.BCM8869X_A0=1
serdes_fabric_clk_freq_in.BCM8869X=2
serdes_fabric_clk_freq_out.BCM8869X=1
serdes_nif_clk_freq_in.BCM8869X=1
serdes_nif_clk_freq_out.BCM8869X=bypass
serdes_fabric_clk_freq_in.BCM8869X=1
serdes_fabric_clk_freq_out.BCM8869X=bypass
dram_phy_tune_mode_on_init.BCM8869X=RUN_TUNE

2
src/sonic-device-data/tests/config_checker
View File

@ -31,7 +31,7 @@ def check_file(file_name):
p = line.split("=", 1)[0]
# Remove trailing chip name "bcm8869x"
p = re.sub(r"\.bcm8869x(_adapter)?$", "", p)
p = re.sub(r"\.bcm8869x(_adapter|_[a-z]\d)?$", "", p)
# Remove trailing unit ".<number>$"
p = re.sub(r"\.[0-9]+$", '', p)
# Remove trailing port name