- Why I did it
On Arista-7050CX3-32S-C32, there are constant stream of errors like following.
Nov 3 21:56:24.415190 str2-7050cx3-acs-06 NOTICE swss#orchagent: :- registerInWdDb: No lossless TC found on port Ethernet68
Which causes:
loganalyzer to claim test failed.
leaving the system without MMU configuration. Which couldn't be good for any IO test.
- How I did it
Added these MMU configuraions are copied from another platform and guaranteed to be incorrect for hwsku Arista-7050CX3-32S-C32.
Adding them so that we have A MMU configuration and the system won't throw a whole bunch of errors and leave MMU unconfigured. The correct MMU configuration will come later.
This configuration is definitely not suitable for testing system performance or QoS behavior.
Signed-off-by: Ying Xie ying.xie@microsoft.com
- How to verify it
Test will have chance to pass. Ran a few test that would fail otherwise.
This PR has a dependency on community change to move PCIe config files from $PLATFORM/plugin folder to $PLATFORM/ folder
- Why I did it
To support PCIed daemon on Mellanox platforms
- How I did it
Add PCIed config yaml files for all Mellanox platforms
Update pmon daemon config files for SimX platforms
We don't need a custom platform reboot on Clearwater2(Ms). They are expected to be rebooted via a normal linux soft reboot.
Remove symlink to the arista common platform reboot for those 2 platforms.
**- Why I did it**
Converted two SP model to single pool model and modified the buffer size.
**- How I did it**
Changed buffer_default settings for all the DellEMC Z9264f HWSKU's.
**- How to verify it**
Check SP register values in NPU shell.
**- Which release branch to backport (provide reason below if selected)**
Need to be cherry picked for 201911 branch.
- Enable thermalctld support for our platforms
- Fix Chassis.get_num_sfp which had an off by one
- Implement read_eeprom and write_eeprom in SfpBase
- Refactor of Psus and PsuSlots. Psus they are now detected and metadata reported
- Improvements to modular support
Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
The `get_serial_number()` method in the ChassisBase and ModuleBase classes was redundant, as the `get_serial()` method is inherited from the DeviceBase class. This method was removed from the base classes in sonic-platform-common and the submodule was updated in https://github.com/Azure/sonic-buildimage/pull/5625.
This PR aligns the existing vendor platform API implementations to remove the `get_serial_number()` methods and ensure the `get_serial()` methods are implemented, if they weren't previously.
Note that this PR does not modify the Dell platform API implementations, as this will be handled as part of https://github.com/Azure/sonic-buildimage/pull/5609
- Make DellEMC platform modules Python3 compliant.
- Change return type of PSU Platform APIs in DellEMC Z9264, S5232 and Thermal Platform APIs in S5232 to 'float'.
- Remove multiple copies of pcisysfs.py.
- PEP8 style changes for utility scripts.
- Build and install Python3 version of sonic_platform package.
- Fix minor Platform API issues.
bring up chassisdb service on sonic switch according to the design in
Distributed Forwarding in VoQ Arch HLD
Signed-off-by: Honggang Xu <hxu@arista.com>
**- Why I did it**
To bring up new ChassisDB service in sonic as designed in ['Distributed forwarding in a VOQ architecture HLD' ](90c1289eaf/doc/chassis/architecture.md).
**- How I did it**
Implement the section 2.3.1 Global DB Organization of the VOQ architecture HLD.
**- How to verify it**
ChassisDB service won't start without chassisdb.conf file on the existing platforms.
ChassisDB service is accessible with global.conf file in the distributed arichitecture.
Signed-off-by: Honggang Xu <hxu@arista.com>
* system health first commit
* system health daemon first commit
* Finish healthd
* Changes due to lower layer logic change
* Get ASIC temperature from TEMPERATURE_INFO table
* Add system health make rule and service files
* fix bugs found during manual test
* Change make file to install system-health library to host
* Set system LED to blink on bootup time
* Caught exceptions in system health checker to make it more robust
* fix issue that fan/psu presence will always be true
* fix issue for external checker
* move system-health service to right after rc-local service
* Set system-health service start after database service
* Get system up time via /proc/uptime
* Provide more information in stat for CLI to use
* fix typo
* Set default category to External for external checker
* If external checker reported OK, save it to stat too
* Trim string for external checker output
* fix issue: PSU voltage check always return OK
* Add unit test cases for system health library
* Fix LGTM warnings
* fix demo comments: 1. get boot up timeout from monit configuration file; 2. set system led in library instead of daemon
* Remove boot_timeout configuration because it will get from monit config file
* Fix argument miss
* fix unit test failure
* fix issue: summary status is not correct
* Fix format issues found in code review
* rename th to threshold to make it clearer
* Fix review comment: 1. add a .dep file for system health; 2. deprecated daemon_base and uses sonic-py-common instead
* Fix unit test failure
* Fix LGTM alert
* Fix LGTM alert
* Fix review comments
* Fix review comment
* 1. Add relevant comments for system health; 2. rename external_checker to user_define_checker
* Ignore check for unknown service type
* Fix unit test issue
* Rename user define checker to user defined checker
* Rename user_define_checkers to user_defined_checkers for configuration file
* Renmae file user_define_checker.py -> user_defined_checker.py
* Fix typo
* Adjust import order for config.py
Co-authored-by: Joe LeVeque <jleveque@users.noreply.github.com>
* Adjust import order for src/system-health/health_checker/hardware_checker.py
Co-authored-by: Joe LeVeque <jleveque@users.noreply.github.com>
* Adjust import order for src/system-health/scripts/healthd
Co-authored-by: Joe LeVeque <jleveque@users.noreply.github.com>
* Adjust import orders in src/system-health/tests/test_system_health.py
* Fix typo
* Add new line after import
* If system health configuration file not exist, healthd should exit
* Fix indent and enable pytest coverage
* Fix typo
* Fix typo
* Remove global logger and use log functions inherited from super class
* Change info level logger to notice level
Co-authored-by: Joe LeVeque <jleveque@users.noreply.github.com>
This is to fix pcie firmware check assert in Broadcom SDK once the SAI changes merges. This will be in the future but adding the soc property in the broadcom config now.
Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
**- Why I did it**
There is error i2c mapping for port 11,12 and port 19, 20.
**- How I did it**
Fix to correct i2c mapping
Co-authored-by: Jostar Yang <jostar_yang@accton.com.tw>
* buildimage: Add gearbox phy device files and a new physyncd docker to support VS gearbox phy feature
* scripts and configuration needed to support a second syncd docker (physyncd)
* physyncd supports gearbox device and phy SAI APIs and runs multiple instances of syncd, one per phy in the device
* support for VS target (sonic-sairedis vslib has been extended to support a virtual BCM81724 gearbox PHY).
HLD is located at b817a12fd8/doc/gearbox/gearbox_mgr_design.md
**- Why I did it**
This work is part of the gearbox phy joint effort between Microsoft and Broadcom, and is based
on multi-switch support in sonic-sairedis.
**- How I did it**
Overall feature was implemented across several projects. The collective pull requests (some in late stages of review at this point):
https://github.com/Azure/sonic-utilities/pull/931 - CLI (merged)
https://github.com/Azure/sonic-swss-common/pull/347 - Minor changes (merged)
https://github.com/Azure/sonic-swss/pull/1321 - gearsyncd, config parsers, changes to orchargent to create gearbox phy on supported systems
https://github.com/Azure/sonic-sairedis/pull/624 - physyncd, virtual BCM81724 gearbox phy added to vslib
**- How to verify it**
In a vslib build:
root@sonic:/home/admin# show gearbox interfaces status
PHY Id Interface MAC Lanes MAC Lane Speed PHY Lanes PHY Lane Speed Line Lanes Line Lane Speed Oper Admin
-------- ----------- --------------- ---------------- --------------- ---------------- ------------ ----------------- ------ -------
1 Ethernet48 121,122,123,124 25G 200,201,202,203 25G 204,205 50G down down
1 Ethernet49 125,126,127,128 25G 206,207,208,209 25G 210,211 50G down down
1 Ethernet50 69,70,71,72 25G 212,213,214,215 25G 216 100G down down
In addition, docker ps | grep phy should show a physyncd docker running.
Signed-off-by: syd.logan@broadcom.com
As part of Platform api testing for multiple platforms, this pull request adds a platform.json file which contains all
the static data for Mellanox-2700 platform. This file would provide all the platform specific data required for testing of all the Platform tests . As part of testing the API's the values of static/default objects within this specific platform file will be compared against the values returned by calling the Platform specific API's in a typical platform test
However in SAI 3.7 default behaviout got changes to 128 Group and 128
Memeber each.
This change is to make sure we are using same ECMP Group/Memeber Per
Group for 3.7 also so that behaviour is consistent.
Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
C64: 32 100G down links and 32 100G up links.
D112C8: 112 50G down links and 8 100G up links.
D24C52: 24 50G down links, 20 100G down links, and 32 100G up links.
D28C50: 28 50G down links, 18 100G down links, and 32 100G up links.
Signed-off-by: Stephen Sun <stephens@nvidia.com>
This include the platform.json for Seastone platform and
individual hwsku.json for each HWSKU
port_config.ini will be removed once the CLI/parser library etc changes are merged
**- What I did**
On boarding DPB feature to Seastone HWSKUs
**- How I did it**
Add platform.json for Seastone and hwsku.json files to relevant HWSKUs.
**- How to verify it**
```
sudo sonic-cfggen -H -k Seastone-DX010 --preset=t1 > config_db.json
sudo config reload config_db.json -y
show interface status:
admin@lnos-x1-a-csw03:~$ show interfaces status
Interface Lanes Speed MTU FEC Alias Vlan Oper Admin Type Asym PFC
----------- --------------- ------- ----- ----- ------- ------ ------ ------- ------ ----------
Ethernet0 65,66,67,68 100G 9100 N/A Eth1/1 routed down up N/A N/A
Ethernet4 69,70,71,72 100G 9100 N/A Eth2/1 routed down up N/A N/A
Ethernet8 73,74,75,76 100G 9100 N/A Eth3/1 routed down up N/A N/A
Ethernet12 77,78,79,80 100G 9100 N/A Eth4/1 routed down up N/A N/A
Ethernet16 33,34,35,36 100G 9100 N/A Eth5/1 routed down up N/A N/A
Ethernet20 37,38,39,40 100G 9100 N/A Eth6/1 routed down up N/A N/A
Ethernet24 41,42,43,44 100G 9100 N/A Eth7/1 routed down up N/A N/A
Ethernet28 45,46,47,48 100G 9100 N/A Eth8/1 routed down up N/A N/A
Ethernet32 49,50,51,52 100G 9100 N/A Eth9/1 routed down up N/A N/A
Ethernet36 53,54,55,56 100G 9100 N/A Eth10/1 routed down up N/A N/A
Ethernet40 57,58,59,60 100G 9100 N/A Eth11/1 routed down up N/A N/A
Ethernet44 61,62,63,64 100G 9100 N/A Eth12/1 routed down up N/A N/A
Ethernet48 81,82,83,84 100G 9100 N/A Eth13/1 routed down up N/A N/A
Ethernet52 85,86,87,88 100G 9100 N/A Eth14/1 routed down up N/A N/A
Ethernet56 89,90,91,92 100G 9100 N/A Eth15/1 routed down up N/A N/A
Ethernet60 93,94,95,96 100G 9100 N/A Eth16/1 routed down up N/A N/A
Ethernet64 97,98,99,100 100G 9100 N/A Eth17/1 routed down up N/A N/A
Ethernet68 101,102,103,104 100G 9100 N/A Eth18/1 routed down up N/A N/A
Ethernet72 105,106,107,108 100G 9100 N/A Eth19/1 routed up up N/A N/A
Ethernet76 109,110,111,112 100G 9100 N/A Eth20/1 routed down up N/A N/A
Ethernet80 1,2,3,4 100G 9100 N/A Eth21/1 routed down up N/A N/A
Ethernet84 5,6,7,8 100G 9100 N/A Eth22/1 routed down up N/A N/A
Ethernet88 9,10,11,12 100G 9100 N/A Eth23/1 routed down up N/A N/A
Ethernet92 13,14,15,16 100G 9100 N/A Eth24/1 routed down up N/A N/A
Ethernet96 17,18,19,20 100G 9100 N/A Eth25/1 routed down up N/A N/A
Ethernet100 21,22,23,24 100G 9100 N/A Eth26/1 routed down up N/A N/A
Ethernet104 25,26,27,28 100G 9100 N/A Eth27/1 routed down up N/A N/A
Ethernet108 29,30,31,32 100G 9100 N/A Eth28/1 routed down up N/A N/A
Ethernet112 113,114,115,116 100G 9100 N/A Eth29/1 routed down up N/A N/A
Ethernet116 117,118,119,120 100G 9100 N/A Eth30/1 routed down up N/A N/A
Ethernet120 121,122,123,124 100G 9100 N/A Eth31/1 routed down up N/A N/A
Ethernet124 125,126,127,128 100G 9100 N/A Eth32/1 routed down up N/A N/A
```
**Breakout to 2x50G:**
```
admin@lnos-x1-a-csw03:~$ sudo config interface breakout Ethernet0 2x50G -y -f
Running Breakout Mode : 1x100G[40G]
Target Breakout Mode : 2x50G
Ports to be deleted :
{
"Ethernet0": "100000"
}
Ports to be added :
{
"Ethernet2": "50000",
"Ethernet0": "50000"
}
After running Logic to limit the impact
Final list of ports to be deleted :
{
"Ethernet0": "100000"
}
Final list of ports to be added :
{
"Ethernet2": "50000",
"Ethernet0": "50000"
}
Loaded below Yang Models
['sonic-acl', 'sonic-extension', 'sonic-interface', 'sonic-loopback-interface', 'sonic-port', 'sonic-portchannel', 'sonic-types', 'sonic-vlan']
Note: Below table(s) have no YANG models:
CONTAINER_FEATURE, BGP_NEIGHBOR, VERSIONS, DEVICE_METADATA, FEATURE, LOCK, BREAKOUT_CFG, CRM,
Below Config can not be verified, It may cause harm to the system
{
"BREAKOUT_CFG": {
"Ethernet0": {
"brkout_mode": "1x100G[40G]"
}
}
}
Do you wish to Continue? [y/N]: y
Breakout process got successfully completed.
Please note loaded setting will be lost after system reboot. To preserve setting, run `config save`.
admin@lnos-x1-a-csw03:~$
admin@lnos-x1-a-csw03:~$
admin@lnos-x1-a-csw03:~$ show interfaces status
Interface Lanes Speed MTU FEC Alias Vlan Oper Admin Type Asym PFC
----------- --------------- ------- ----- ----- ------- ------ ------ ------- ------ ----------
Ethernet0 65,66 50G N/A N/A Eth1/1 routed down up N/A N/A
Ethernet2 67,68 50G 9100 N/A Eth1/3 routed down up N/A N/A
admin@lnos-x1-a-csw03:~$ bcmcmd ps
ps
ena/ speed/ link auto STP lrn inter max cut loop
port link Lns duplex scan neg? state pause discrd ops face frame thru? back
xe0( 68) down 2 50G FD SW No Forward None FA KR2 9412 No
xe1( 69) !ena 1 - SW No Forward None FA None 9122 No
```
**Breakout to 4x25G[10G]:**
```
admin@lnos-x1-a-csw03:~$ sudo config interface breakout Ethernet0 4x25G[10G] -y -f
Running Breakout Mode : 2x50G
Target Breakout Mode : 4x25G[10G]
Ports to be deleted :
{
"Ethernet2": "50000",
"Ethernet0": "50000"
}
Ports to be added :
{
"Ethernet2": "25000",
"Ethernet3": "25000",
"Ethernet0": "25000",
"Ethernet1": "25000"
}
After running Logic to limit the impact
Final list of ports to be deleted :
{
"Ethernet2": "50000",
"Ethernet0": "50000"
}
Final list of ports to be added :
{
"Ethernet2": "25000",
"Ethernet3": "25000",
"Ethernet0": "25000",
"Ethernet1": "25000"
}
Loaded below Yang Models
['sonic-acl', 'sonic-extension', 'sonic-interface', 'sonic-loopback-interface', 'sonic-port', 'sonic-portchannel', 'sonic-types', 'sonic-vlan']
Note: Below table(s) have no YANG models:
CONTAINER_FEATURE, BGP_NEIGHBOR, VERSIONS, DEVICE_METADATA, FEATURE, LOCK, BREAKOUT_CFG, CRM,
Below Config can not be verified, It may cause harm to the system
{
"BREAKOUT_CFG": {
"Ethernet0": {
"brkout_mode": "2x50G"
}
}
}
Do you wish to Continue? [y/N]: y
Breakout process got successfully completed.
Please note loaded setting will be lost after system reboot. To preserve setting, run `config save`.
admin@lnos-x1-a-csw03:~$ show interfaces status
Interface Lanes Speed MTU FEC Alias Vlan Oper Admin Type Asym PFC
----------- --------------- ------- ----- ----- ------- ------ ------ ------- ------ ----------
Ethernet0 65 25G N/A N/A Eth1/1 routed down up N/A N/A
Ethernet1 66 25G 9100 N/A Eth1/2 routed down up N/A N/A
Ethernet2 67 25G N/A N/A Eth1/3 routed down up N/A N/A
Ethernet3 68 25G 9100 N/A Eth1/4 routed down up N/A N/A
admin@lnos-x1-a-csw03:~$ bcmcmd ps
ps
ena/ speed/ link auto STP lrn inter max cut loop
port link Lns duplex scan neg? state pause discrd ops face frame thru? back
xe0( 68) down 1 25G FD SW No Forward None FA KR 9412 No
xe1( 69) down 1 25G FD SW No Forward None FA KR 9122 No
xe2( 70) down 1 25G FD SW No Forward None FA KR 9412 No
xe3( 71) down 1 25G FD SW No Forward None FA KR 9122 No
```
**Breakin back to 1x100G[40G]:**
```
admin@lnos-x1-a-csw03:~$ sudo config interface breakout Ethernet0 1x10G[40G] -y -f
[ERROR] Target mode 1x10G[40G] is not available for the port Ethernet0
Aborted!
admin@lnos-x1-a-csw03:~$ sudo config interface breakout Ethernet0 1x100G[40G] -y -f
Running Breakout Mode : 4x25G[10G]
Target Breakout Mode : 1x100G[40G]
Ports to be deleted :
{
"Ethernet2": "25000",
"Ethernet3": "25000",
"Ethernet0": "25000",
"Ethernet1": "25000"
}
Ports to be added :
{
"Ethernet0": "100000"
}
After running Logic to limit the impact
Final list of ports to be deleted :
{
"Ethernet2": "25000",
"Ethernet3": "25000",
"Ethernet0": "25000",
"Ethernet1": "25000"
}
Final list of ports to be added :
{
"Ethernet0": "100000"
}
Loaded below Yang Models
['sonic-acl', 'sonic-extension', 'sonic-interface', 'sonic-loopback-interface', 'sonic-port', 'sonic-portchannel', 'sonic-types', 'sonic-vlan']
Note: Below table(s) have no YANG models:
CONTAINER_FEATURE, BGP_NEIGHBOR, VERSIONS, DEVICE_METADATA, FEATURE, LOCK, FLEX_COUNTER_TABLE, BREAKOUT_CFG, CRM,
Below Config can not be verified, It may cause harm to the system
{
"BREAKOUT_CFG": {
"Ethernet0": {
"brkout_mode": "4x25G[10G]"
}
}
}
Do you wish to Continue? [y/N]: y
Breakout process got successfully completed.
Please note loaded setting will be lost after system reboot. To preserve setting, run `config save`.
admin@lnos-x1-a-csw03:~$ show interfaces status
Interface Lanes Speed MTU FEC Alias Vlan Oper Admin Type Asym PFC
----------- --------------- ------- ----- ----- ------- ------ ------ ------- ------ ----------
Ethernet0 65,66,67,68 100G N/A N/A Eth1/1 routed down up N/A N/A
admin@lnos-x1-a-csw03:~$ bcmcmd ps
ps
ena/ speed/ link auto STP lrn inter max cut loop
port link Lns duplex scan neg? state pause discrd ops face frame thru? back
ce0( 68) down 4 100G FD SW No Forward None FA KR4 9412 No
xe0( 69) !ena 1 - SW No Forward None FA None 9122 No
xe1( 70) !ena 2 - SW No Forward None FA None 9412 No
xe2( 71) !ena 1 - SW No Forward None FA None 9122 No
```
Signed-off-by: Zhenggen Xu <zxu@linkedin.com>
Refactor SFP reset, low power get/set API, and plugins with new SDK SX APIs. Previously they were calling SDK SXD APIs which have glibc dependency because of shared memory usage.
Remove implementation "set_power_override", "tx_disable_channel", "tx_disable" which using SXD APIs, once related SDK SX API available, will add them back based on new SDK SX APIs.
- Merge chassis codebase upstream
- Add support for Otterlake supervisor
- Add support for NorthFace and Camp chassis
- Add support for Eldridge, Dragonfly and Brooks fabrics
- Add support for Clearwater2 and Clearwater2Ms linecards
- Add new arista Cli to power on/off cards
- Add new arista show Cli to inspect supervisor, chassis, fabrics and linecards
as needed by SAI 3.7 and above. Without this change
Warmboot fails from 3.5 to 3.7 as Braodcoam Datastructure
gets corrupted after warm-boot.
Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
Modify port_config.ini files multi-asic vs platform. Changes done:
- Add new columns: index, asic_port_name, role(Int/Ext)
- Modify alias of interface names. Alias should match the interface names present in minigraph file.
Signed-off-by: SuvarnaMeenakshi <sumeenak@microsoft.com>
Calculate pool size in t1 as 24 * downlink port + 8 * uplink port
- Take both port and peer MTU into account when calculating headroom
- Worst case factor is decreased to 50%
- Mellanox-SN2700-C28D8 t0, assume 48 * 50G/5m + 8 * 100G/40m ports
- Mellanox-SN2700 (C32)
- t0: 16 * 100G/5m + 16 * 100G/40m
- t1: 16 * 100G/40m + 16 * 100G/300m
Signed-off-by: Stephen Sun <stephens@mellanox.com>
Co-authored-by: Stephen Sun <stephens@mellanox.com>
summary of E530 platfrom:
- CPU: CTC5236, arm64
- LAN switch chip set: CENTEC CTC7132 (TsingMa). TsingMa is a purpose built device to address the challenge in the recent network evolution such as Cloud computing. CTC7132 provides 440Gbps I/O bandwidth and 400Gcore bandwidth, the CTC7132 family combines a feature-rich switch core and an embedded ARM A53 CPU Core running at 800MHz/1.2GHz. CTC7132 supports a variety of port configurations, such as QSGMII and USXGMII-M, providing full-rate port capability from 100M to 100G.
- device E530-48T4X: 48 * 10/100/1000 Base-T Ports, 4 * 10GE SFP+ Ports.
- device E530-24X2C: 24 * 10 GE SFP+ Ports, 2 * 100GE QSFP28 Ports.
add new files in three directories:
device/centec/arm64-centec_e530_24x2c-r0
device/centec/arm64-centec_e530_48t4x_p-r0
platform/centec-arm64
Co-authored-by: taocy <taocy2@centecnetworks.com>
Co-authored-by: Gu Xianghong <gxh2001757@163.com>
Co-authored-by: shil <shil@centecnetworks.com>
