[device/celestica]: Update DX010 reboot cause API (#4678)
- Add more cases support in DX010 reboot cause API
- Add Thermal Overload reboot cause support
- Add new Watchdog reboot cause support
This commit is contained in:
Wirut Getbamrung
GitHub
parent
ae9a86fac4
commit
47316de5c4
@ -8,4 +8,6 @@ MINSTART=13-002e/pwm1=89 13-002e/pwm2=89 13-002e/pwm3=89 13-002e/pwm4=89 13-002e
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MINSTOP=13-002e/pwm1=89 13-002e/pwm2=89 13-002e/pwm3=89 13-002e/pwm4=89 13-002e/pwm5=89 13-004d/pwm1=89 13-004d/pwm2=89 13-004d/pwm3=89 13-004d/pwm4=89 13-004d/pwm5=89
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MINPWM=13-002e/pwm1=89 13-002e/pwm2=89 13-002e/pwm3=89 13-002e/pwm4=89 13-002e/pwm5=89 13-004d/pwm1=89 13-004d/pwm2=89 13-004d/pwm3=89 13-004d/pwm4=89 13-004d/pwm5=89
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MAXPWM=13-002e/pwm1=255 13-002e/pwm2=255 13-002e/pwm3=255 13-002e/pwm4=255 13-002e/pwm5=255 13-004d/pwm1=255 13-004d/pwm2=255 13-004d/pwm3=255 13-004d/pwm4=255 13-004d/pwm5=255
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THYST=13-002e/pwm1=3 13-002e/pwm2=3 13-002e/pwm3=3 13-002e/pwm4=3 13-002e/pwm5=3 13-004d/pwm1=3 13-004d/pwm2=3 13-004d/pwm3=3 13-004d/pwm4=3 13-004d/pwm5=3
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THYST=13-002e/pwm1=3 13-002e/pwm2=3 13-002e/pwm3=3 13-002e/pwm4=3 13-002e/pwm5=3 13-004d/pwm1=3 13-004d/pwm2=3 13-004d/pwm3=3 13-004d/pwm4=3 13-004d/pwm5=3
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MAXTEMPCRIT=/sys/bus/i2c/devices/7-004a/hwmon/hwmon*/temp1_input=65 /sys/bus/i2c/devices/14-0048/hwmon/hwmon*/temp1_input=75
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MAXTEMPTYPE=/sys/bus/i2c/devices/7-004a/hwmon/hwmon*/temp1_input=ASIC /sys/bus/i2c/devices/14-0048/hwmon/hwmon*/temp1_input=CPU
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@ -9,4 +9,5 @@ MINSTOP=13-002e/pwm1=89 13-002e/pwm2=89 13-002e/pwm3=89 13-002e/pwm4=89 13-002e/
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MINPWM=13-002e/pwm1=89 13-002e/pwm2=89 13-002e/pwm3=89 13-002e/pwm4=89 13-002e/pwm5=89 13-004d/pwm1=89 13-004d/pwm2=89 13-004d/pwm3=89 13-004d/pwm4=89 13-004d/pwm5=89
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MAXPWM=13-002e/pwm1=255 13-002e/pwm2=255 13-002e/pwm3=255 13-002e/pwm4=255 13-002e/pwm5=255 13-004d/pwm1=255 13-004d/pwm2=255 13-004d/pwm3=255 13-004d/pwm4=255 13-004d/pwm5=255
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THYST=13-002e/pwm1=3 13-002e/pwm2=3 13-002e/pwm3=3 13-002e/pwm4=3 13-002e/pwm5=3 13-004d/pwm1=3 13-004d/pwm2=3 13-004d/pwm3=3 13-004d/pwm4=3 13-004d/pwm5=3
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MAXTEMPCRIT=/sys/bus/i2c/devices/7-004a/hwmon/hwmon*/temp1_input=75 /sys/bus/i2c/devices/14-0048/hwmon/hwmon*/temp1_input=75
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MAXTEMPTYPE=/sys/bus/i2c/devices/7-004a/hwmon/hwmon*/temp1_input=ASIC /sys/bus/i2c/devices/14-0048/hwmon/hwmon*/temp1_input=CPU
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@ -1,2 +1,2 @@
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__all__ = ["platform", "chassis"]
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from sonic_platform import *
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import chassis
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import platform
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@ -23,9 +23,9 @@ NUM_SFP = 32
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NUM_COMPONENT = 5
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RESET_REGISTER = "0x103"
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HOST_REBOOT_CAUSE_PATH = "/host/reboot-cause/"
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PMON_REBOOT_CAUSE_PATH = "/usr/share/sonic/platform/api_files/reboot-cause/"
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REBOOT_CAUSE_FILE = "reboot-cause.txt"
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PREV_REBOOT_CAUSE_FILE = "previous-reboot-cause.txt"
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GETREG_PATH = "/sys/devices/platform/dx010_cpld/getreg"
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HOST_CHK_CMD = "docker > /dev/null 2>&1"
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@ -118,35 +118,38 @@ class Chassis(ChassisBase):
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one of the predefined strings in this class. If the first string
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is "REBOOT_CAUSE_HARDWARE_OTHER", the second string can be used
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to pass a description of the reboot cause.
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REBOOT_CAUSE_POWER_LOSS = "Power Loss"
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REBOOT_CAUSE_THERMAL_OVERLOAD_CPU = "Thermal Overload: CPU"
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REBOOT_CAUSE_THERMAL_OVERLOAD_ASIC = "Thermal Overload: ASIC"
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REBOOT_CAUSE_THERMAL_OVERLOAD_OTHER = "Thermal Overload: Other"
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REBOOT_CAUSE_INSUFFICIENT_FAN_SPEED = "Insufficient Fan Speed"
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REBOOT_CAUSE_WATCHDOG = "Watchdog"
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REBOOT_CAUSE_HARDWARE_OTHER = "Hardware - Other"
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REBOOT_CAUSE_NON_HARDWARE = "Non-Hardware"
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"""
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description = 'None'
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reboot_cause = self.REBOOT_CAUSE_HARDWARE_OTHER
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reboot_cause_path = (HOST_REBOOT_CAUSE_PATH + REBOOT_CAUSE_FILE) if self.is_host else PMON_REBOOT_CAUSE_PATH + REBOOT_CAUSE_FILE
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prev_reboot_cause_path = (HOST_REBOOT_CAUSE_PATH + PREV_REBOOT_CAUSE_FILE) if self.is_host else PMON_REBOOT_CAUSE_PATH + PREV_REBOOT_CAUSE_FILE
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hw_reboot_cause = self._component_list[0].get_register_value(RESET_REGISTER)
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reboot_cause_path = (HOST_REBOOT_CAUSE_PATH + REBOOT_CAUSE_FILE)
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sw_reboot_cause = self._api_helper.read_txt_file(
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reboot_cause_path) or "Unknown"
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prev_sw_reboot_cause = self._api_helper.read_txt_file(
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prev_reboot_cause_path) or "Unknown"
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hw_reboot_cause = self._api_helper.get_cpld_reg_value(
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GETREG_PATH, RESET_REGISTER)
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if sw_reboot_cause == "Unknown" and (prev_sw_reboot_cause == "Unknown" or prev_sw_reboot_cause == self.REBOOT_CAUSE_POWER_LOSS) and hw_reboot_cause == "0x11":
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reboot_cause = self.REBOOT_CAUSE_POWER_LOSS
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elif sw_reboot_cause != "Unknown" and hw_reboot_cause == "0x11":
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reboot_cause = self.REBOOT_CAUSE_NON_HARDWARE
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description = sw_reboot_cause
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elif prev_reboot_cause_path != "Unknown" and hw_reboot_cause == "0x11":
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reboot_cause = self.REBOOT_CAUSE_NON_HARDWARE
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description = prev_sw_reboot_cause
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elif hw_reboot_cause == "0x22":
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reboot_cause = self.REBOOT_CAUSE_WATCHDOG,
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else:
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reboot_cause = self.REBOOT_CAUSE_HARDWARE_OTHER
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description = 'Unknown reason'
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prev_reboot_cause = {
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'0x11': (self.REBOOT_CAUSE_POWER_LOSS, 'Power on reset'),
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'0x22': (self.REBOOT_CAUSE_HARDWARE_OTHER, 'CPLD_WD_RESET'),
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'0x33': (self.REBOOT_CAUSE_HARDWARE_OTHER, 'Power cycle reset triggered by CPU'),
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'0x44': (self.REBOOT_CAUSE_HARDWARE_OTHER, 'Power cycle reset triggered by reset button'),
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'0x55': (self.REBOOT_CAUSE_THERMAL_OVERLOAD_CPU, ''),
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'0x66': (self.REBOOT_CAUSE_THERMAL_OVERLOAD_ASIC, ''),
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'0x77': (self.REBOOT_CAUSE_WATCHDOG, '')
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}.get(hw_reboot_cause, (self.REBOOT_CAUSE_HARDWARE_OTHER, 'Unknown reason'))
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return (reboot_cause, description)
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if sw_reboot_cause != 'Unknown' and hw_reboot_cause == '0x11':
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prev_reboot_cause = (
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self.REBOOT_CAUSE_NON_HARDWARE, sw_reboot_cause)
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return prev_reboot_cause
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##############################################################
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######################## SFP methods #########################
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@ -229,9 +232,9 @@ class Chassis(ChassisBase):
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def get_presence(self):
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"""
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Retrieves the presence of the PSU
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Retrieves the presence of the Chassis
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Returns:
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bool: True if PSU is present, False if not
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bool: True if Chassis is present, False if not
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"""
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return True
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@ -70,6 +70,19 @@ class APIHelper():
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pass
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return None
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def write_txt_file(self, file_path, value):
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try:
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with open(file_path, 'w') as fd:
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fd.write(str(value))
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except Exception:
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return False
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return True
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def get_cpld_reg_value(self, getreg_path, register):
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cmd = "echo {1} > {0}; cat {0}".format(getreg_path, register)
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status, result = self.run_command(cmd)
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return result if status else None
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def ipmi_raw(self, netfn, cmd):
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status = True
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result = ""
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@ -7,115 +7,79 @@
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#
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#############################################################################
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import ctypes
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import fcntl
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import os
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import subprocess
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import time
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import array
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try:
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from sonic_platform_base.watchdog_base import WatchdogBase
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from helper import APIHelper
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except ImportError as e:
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raise ImportError(str(e) + "- required module not found")
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""" ioctl constants """
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IO_WRITE = 0x40000000
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IO_READ = 0x80000000
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IO_READ_WRITE = 0xC0000000
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IO_SIZE_INT = 0x00040000
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IO_SIZE_40 = 0x00280000
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IO_TYPE_WATCHDOG = ord('W') << 8
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WDR_INT = IO_READ | IO_SIZE_INT | IO_TYPE_WATCHDOG
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WDR_40 = IO_READ | IO_SIZE_40 | IO_TYPE_WATCHDOG
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WDWR_INT = IO_READ_WRITE | IO_SIZE_INT | IO_TYPE_WATCHDOG
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""" Watchdog ioctl commands """
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WDIOC_GETSUPPORT = 0 | WDR_40
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WDIOC_GETSTATUS = 1 | WDR_INT
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WDIOC_GETBOOTSTATUS = 2 | WDR_INT
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WDIOC_GETTEMP = 3 | WDR_INT
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WDIOC_SETOPTIONS = 4 | WDR_INT
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WDIOC_KEEPALIVE = 5 | WDR_INT
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WDIOC_SETTIMEOUT = 6 | WDWR_INT
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WDIOC_GETTIMEOUT = 7 | WDR_INT
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WDIOC_SETPRETIMEOUT = 8 | WDWR_INT
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WDIOC_GETPRETIMEOUT = 9 | WDR_INT
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WDIOC_GETTIMELEFT = 10 | WDR_INT
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""" Watchdog status constants """
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WDIOS_DISABLECARD = 0x0001
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WDIOS_ENABLECARD = 0x0002
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PLATFORM_CPLD_PATH = '/sys/devices/platform/dx010_cpld'
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GETREG_FILE = 'getreg'
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SETREG_FILE = 'setreg'
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WDT_ENABLE_REG = '0x141'
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WDT_TIMER_L_BIT_REG = '0x142'
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WDT_TIMER_M_BIT_REG = '0x143'
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WDT_TIMER_H_BIT_REG = '0x144'
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WDT_KEEP_ALVIVE_REG = '0x145'
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ENABLE_CMD = '0x1'
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DISABLE_CMD = '0x0'
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WDT_COMMON_ERROR = -1
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WD_MAIN_IDENTITY = "iTCO_wdt"
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WDT_SYSFS_PATH = "/sys/class/watchdog/"
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class Watchdog(WatchdogBase):
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def __init__(self):
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# Init helper
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self._api_helper = APIHelper()
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# Init cpld reg path
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self.setreg_path = os.path.join(PLATFORM_CPLD_PATH, SETREG_FILE)
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self.getreg_path = os.path.join(PLATFORM_CPLD_PATH, GETREG_FILE)
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self.watchdog, self.wdt_main_dev_name = self._get_wdt()
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self.status_path = "/sys/class/watchdog/%s/status" % self.wdt_main_dev_name
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self.state_path = "/sys/class/watchdog/%s/state" % self.wdt_main_dev_name
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self.timeout_path = "/sys/class/watchdog/%s/timeout" % self.wdt_main_dev_name
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# Set default value
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self._disable()
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self.armed = False
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self.timeout = self._gettimeout(self.timeout_path)
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def _is_wd_main(self, dev):
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"""
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Checks watchdog identity
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"""
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identity = self._read_file(
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"{}/{}/identity".format(WDT_SYSFS_PATH, dev))
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return identity == WD_MAIN_IDENTITY
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def _get_wdt(self):
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"""
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Retrieves watchdog device
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"""
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wdt_main_dev_list = [dev for dev in os.listdir(
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"/dev/") if dev.startswith("watchdog") and self._is_wd_main(dev)]
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if not wdt_main_dev_list:
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return None
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wdt_main_dev_name = wdt_main_dev_list[0]
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watchdog_device_path = "/dev/{}".format(wdt_main_dev_name)
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watchdog = os.open(watchdog_device_path, os.O_RDWR)
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return watchdog, wdt_main_dev_name
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def _read_file(self, file_path):
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"""
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Read text file
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"""
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try:
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with open(file_path, "r") as fd:
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txt = fd.read()
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except IOError:
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return WDT_COMMON_ERROR
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return txt.strip()
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self.timeout = self._gettimeout()
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def _enable(self):
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"""
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Turn on the watchdog timer
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"""
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req = array.array('h', [WDIOS_ENABLECARD])
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fcntl.ioctl(self.watchdog, WDIOC_SETOPTIONS, req, False)
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# echo 0x141 0x1 > /sys/devices/platform/dx010_cpld/setreg
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enable_val = '{} {}'.format(WDT_ENABLE_REG, ENABLE_CMD)
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return self._api_helper.write_txt_file(self.setreg_path, enable_val)
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def _disable(self):
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"""
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Turn off the watchdog timer
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"""
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req = array.array('h', [WDIOS_DISABLECARD])
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fcntl.ioctl(self.watchdog, WDIOC_SETOPTIONS, req, False)
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# echo 0x141 0x0 > /sys/devices/platform/dx010_cpld/setreg
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disable_val = '{} {}'.format(WDT_ENABLE_REG, DISABLE_CMD)
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return self._api_helper.write_txt_file(self.setreg_path, disable_val)
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def _keepalive(self):
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"""
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Keep alive watchdog timer
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"""
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fcntl.ioctl(self.watchdog, WDIOC_KEEPALIVE)
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# echo 0x145 0x1 > /sys/devices/platform/dx010_cpld/setreg
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enable_val = '{} {}'.format(WDT_KEEP_ALVIVE_REG, ENABLE_CMD)
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return self._api_helper.write_txt_file(self.setreg_path, enable_val)
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def _get_level_hex(self, sub_hex):
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sub_hex_str = sub_hex.replace("x", "0")
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return hex(int(sub_hex_str, 16))
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def _seconds_to_lmh_hex(self, seconds):
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ms = seconds*1000 # calculate timeout in ms format
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hex_str = hex(ms)
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l = self._get_level_hex(hex_str[-2:])
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m = self._get_level_hex(hex_str[-4:-2])
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h = self._get_level_hex(hex_str[-6:-4])
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return (l, m, h)
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def _settimeout(self, seconds):
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"""
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@ -123,29 +87,35 @@ class Watchdog(WatchdogBase):
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@param seconds - timeout in seconds
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@return is the actual set timeout
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"""
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req = array.array('I', [seconds])
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fcntl.ioctl(self.watchdog, WDIOC_SETTIMEOUT, req, True)
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return int(req[0])
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# max = 0xffffff = 16777.215 seconds
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def _gettimeout(self, timeout_path):
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(l, m, h) = self._seconds_to_lmh_hex(seconds)
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set_h_val = '{} {}'.format(WDT_TIMER_H_BIT_REG, h)
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set_m_val = '{} {}'.format(WDT_TIMER_M_BIT_REG, m)
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set_l_val = '{} {}'.format(WDT_TIMER_L_BIT_REG, l)
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self._api_helper.write_txt_file(self.setreg_path, set_h_val)
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self._api_helper.write_txt_file(self.setreg_path, set_m_val)
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self._api_helper.write_txt_file(self.setreg_path, set_l_val)
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return seconds
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def _gettimeout(self):
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"""
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Get watchdog timeout
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@return watchdog timeout
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"""
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req = array.array('I', [0])
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fcntl.ioctl(self.watchdog, WDIOC_GETTIMEOUT, req, True)
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return int(req[0])
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h_bit = self._api_helper.get_cpld_reg_value(
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self.getreg_path, WDT_TIMER_H_BIT_REG)
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m_bit = self._api_helper.get_cpld_reg_value(
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self.getreg_path, WDT_TIMER_M_BIT_REG)
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l_bit = self._api_helper.get_cpld_reg_value(
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self.getreg_path, WDT_TIMER_L_BIT_REG)
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def _gettimeleft(self):
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"""
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Get time left before watchdog timer expires
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@return time left in seconds
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"""
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req = array.array('I', [0])
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fcntl.ioctl(self.watchdog, WDIOC_GETTIMELEFT, req, True)
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return int(req[0])
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hex_time = '0x{}{}{}'.format(h_bit[2:], m_bit[2:], l_bit[2:])
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ms = int(hex_time, 16)
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return int(float(ms)/1000)
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#################################################################
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@ -169,12 +139,15 @@ class Watchdog(WatchdogBase):
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try:
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if self.timeout != seconds:
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self.timeout = self._settimeout(seconds)
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if self.armed:
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self._keepalive()
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else:
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self._enable()
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self.armed = True
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ret = self.timeout
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self.arm_timestamp = time.time()
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except IOError as e:
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pass
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@ -215,19 +188,4 @@ class Watchdog(WatchdogBase):
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watchdog timer. If the watchdog is not armed, returns -1.
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"""
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timeleft = WDT_COMMON_ERROR
|
||||
|
||||
if self.armed:
|
||||
try:
|
||||
timeleft = self._gettimeleft()
|
||||
except IOError:
|
||||
pass
|
||||
|
||||
return timeleft
|
||||
|
||||
def __del__(self):
|
||||
"""
|
||||
Close watchdog
|
||||
"""
|
||||
|
||||
os.close(self.watchdog)
|
||||
return int(self.timeout - (time.time() - self.arm_timestamp)) if self.armed else WDT_COMMON_ERROR
|
||||
|
||||
@ -3,6 +3,7 @@ dx010/cfg/dx010-modules.conf etc/modules-load.d
|
||||
dx010/systemd/platform-modules-dx010.service lib/systemd/system
|
||||
dx010/scripts/fancontrol.sh etc/init.d
|
||||
dx010/scripts/fancontrol.service lib/systemd/system
|
||||
dx010/scripts/thermal_overload_control.sh usr/local/bin
|
||||
services/fancontrol/fancontrol usr/local/bin
|
||||
dx010/modules/sonic_platform-1.0-py2-none-any.whl usr/share/sonic/device/x86_64-cel_seastone-r0
|
||||
services/platform_api/platform_api_mgnt.sh usr/local/bin
|
||||
|
||||
@ -76,42 +76,52 @@
|
||||
#define PORT_SFPP1 33
|
||||
#define PORT_SFPP2 34
|
||||
|
||||
#define PORT_ID_BANK1 0x210
|
||||
#define PORT_ID_BANK2 0x290
|
||||
#define PORT_ID_BANK3 0x390
|
||||
|
||||
#define OPCODE_ID_BANK1 0x211
|
||||
#define OPCODE_ID_BANK2 0x291
|
||||
#define OPCODE_ID_BANK3 0x391
|
||||
#define CPLD_I2C_CLK_100Khz_BIT BIT(6)
|
||||
#define CPLD_I2C_DATA_SZ_MASK GENMASK(7,4)
|
||||
#define CPLD_I2C_CMD_SZ_MASK GENMASK(1,0)
|
||||
#define CPLD_I2C_ERR BIT(7)
|
||||
#define CPLD_I2C_BUSY BIT(6)
|
||||
#define CPLD_I2C_RST_BIT BIT(0)
|
||||
#define CPLD_I2C_RESET 0
|
||||
#define CPLD_I2C_UNRESET 1
|
||||
#define CPLD_I2C_DATA_SZ_MAX 8
|
||||
#define CPLD_I2C_CMD_SZ_MAX 3
|
||||
|
||||
#define DEVADDR_ID_BANK1 0x212
|
||||
#define DEVADDR_ID_BANK2 0x292
|
||||
#define DEVADDR_ID_BANK3 0x392
|
||||
|
||||
#define CMDBYT_ID_BANK1 0x213
|
||||
#define CMDBYT_ID_BANK2 0x293
|
||||
#define CMDBYT_ID_BANK3 0x393
|
||||
#define CPLD_I2C_BANK1_BASE 0x210
|
||||
#define CPLD_I2C_BANK2_BASE 0x290
|
||||
#define CPLD_I2C_BANK3_BASE 0x390
|
||||
|
||||
#define WRITE_ID_BANK1 0x220
|
||||
#define WRITE_ID_BANK2 0x2A0
|
||||
#define WRITE_ID_BANK3 0x3A0
|
||||
#define I2C_PORT_ID 0x0
|
||||
#define I2C_OPCODE 0x1
|
||||
#define I2C_DEV_ADDR 0x2
|
||||
#define I2C_CMD_BYT0 0x3
|
||||
#define I2C_SSR 0x6
|
||||
#define I2C_WRITE_DATA 0x10
|
||||
#define I2C_READ_DATA 0x20
|
||||
|
||||
#define READ_ID_BANK1 0x230
|
||||
#define READ_ID_BANK2 0x2B0
|
||||
#define READ_ID_BANK3 0x3B0
|
||||
|
||||
#define SSRR_ID_BANK1 0x216
|
||||
#define SSRR_ID_BANK2 0x296
|
||||
#define SSRR_ID_BANK3 0x396
|
||||
|
||||
#define HST_CNTL2_QUICK 0x00
|
||||
#define HST_CNTL2_BYTE 0x01
|
||||
#define HST_CNTL2_BYTE_DATA 0x02
|
||||
#define HST_CNTL2_WORD_DATA 0x03
|
||||
#define HST_CNTL2_BLOCK 0x05
|
||||
/*
|
||||
* private data to send to I2C core
|
||||
*/
|
||||
struct current_xfer {
|
||||
u8 addr;
|
||||
u8 cmd[CPLD_I2C_CMD_SZ_MAX];
|
||||
u8 cmd_len;
|
||||
u8 data_len;
|
||||
union i2c_smbus_data *data;
|
||||
};
|
||||
|
||||
/*
|
||||
* private data of I2C adapter
|
||||
* base_addr: Base address of this I2C adapter core.
|
||||
* port_id: The port ID, use to mux an i2c core to a font panel port.
|
||||
* current_xfer: The struct carry current data setup of current smbus transfer.
|
||||
*/
|
||||
struct dx010_i2c_data {
|
||||
int base_addr;
|
||||
int portid;
|
||||
struct current_xfer curr_xfer;
|
||||
};
|
||||
|
||||
struct dx010_cpld_data {
|
||||
@ -364,179 +374,210 @@ static struct platform_device cel_dx010_lpc_dev = {
|
||||
}
|
||||
};
|
||||
|
||||
// TODO: Refactoring this function with helper functions.
|
||||
static s32 cpld_smbus_transfer(struct dx010_i2c_data *priv) {
|
||||
|
||||
/**
|
||||
* Read eeprom of QSFP device.
|
||||
* @param a i2c adapter.
|
||||
* @param addr address to read.
|
||||
* @param new_data QSFP port number struct.
|
||||
* @param cmd i2c command.
|
||||
* @return 0 if not error, else the error code.
|
||||
*/
|
||||
static int i2c_read_eeprom(struct i2c_adapter *a, u16 addr,
|
||||
struct dx010_i2c_data *new_data, u8 cmd, union i2c_smbus_data *data){
|
||||
u8 val;
|
||||
s32 error;
|
||||
unsigned long ioBase;
|
||||
short portid, opcode, devaddr, cmdbyte0, ssr, writedata, readdata;
|
||||
union i2c_smbus_data *data;
|
||||
|
||||
u32 reg;
|
||||
int ioBase=0;
|
||||
char byte;
|
||||
short temp;
|
||||
short portid, opcode, devaddr, cmdbyte0, ssrr, writedata, readdata;
|
||||
__u16 word_data;
|
||||
int error = -EIO;
|
||||
error = -EIO;
|
||||
|
||||
mutex_lock(&cpld_data->cpld_lock);
|
||||
|
||||
if (((new_data->portid >= PORT_BANK1_START)
|
||||
&& (new_data->portid <= PORT_BANK1_END))
|
||||
|| (new_data->portid == PORT_SFPP1)
|
||||
|| (new_data->portid == PORT_SFPP2))
|
||||
{
|
||||
portid = PORT_ID_BANK1;
|
||||
opcode = OPCODE_ID_BANK1;
|
||||
devaddr = DEVADDR_ID_BANK1;
|
||||
cmdbyte0 = CMDBYT_ID_BANK1;
|
||||
ssrr = SSRR_ID_BANK1;
|
||||
writedata = WRITE_ID_BANK1;
|
||||
readdata = READ_ID_BANK1;
|
||||
}else if ((new_data->portid >= PORT_BANK2_START) && (new_data->portid <= PORT_BANK2_END)){
|
||||
portid = PORT_ID_BANK2;
|
||||
opcode = OPCODE_ID_BANK2;
|
||||
devaddr = DEVADDR_ID_BANK2;
|
||||
cmdbyte0 = CMDBYT_ID_BANK2;
|
||||
ssrr = SSRR_ID_BANK2;
|
||||
writedata = WRITE_ID_BANK2;
|
||||
readdata = READ_ID_BANK2;
|
||||
}else if ((new_data->portid >= PORT_BANK3_START) && (new_data->portid <= PORT_BANK3_END)){
|
||||
portid = PORT_ID_BANK3;
|
||||
opcode = OPCODE_ID_BANK3;
|
||||
devaddr = DEVADDR_ID_BANK3;
|
||||
cmdbyte0 = CMDBYT_ID_BANK3;
|
||||
ssrr = SSRR_ID_BANK3;
|
||||
writedata = WRITE_ID_BANK3;
|
||||
readdata = READ_ID_BANK3;
|
||||
}else{
|
||||
/* Invalid parameter! */
|
||||
error = -EINVAL;
|
||||
goto exit;
|
||||
}
|
||||
ioBase = priv->base_addr;
|
||||
data = priv->curr_xfer.data;
|
||||
|
||||
while ((inb(ioBase + ssrr) & 0x40));
|
||||
if ((inb(ioBase + ssrr) & 0x80) == 0x80) {
|
||||
error = -EIO;
|
||||
/* Read error reset the port */
|
||||
outb(0x00, ioBase + ssrr);
|
||||
udelay(3000);
|
||||
outb(0x01, ioBase + ssrr);
|
||||
goto exit;
|
||||
}
|
||||
portid = ioBase + I2C_PORT_ID;
|
||||
opcode = ioBase + I2C_OPCODE;
|
||||
devaddr = ioBase + I2C_DEV_ADDR;
|
||||
cmdbyte0 = ioBase + I2C_CMD_BYT0;
|
||||
ssr = ioBase + I2C_SSR;
|
||||
writedata = ioBase + I2C_WRITE_DATA;
|
||||
readdata = ioBase + I2C_READ_DATA;
|
||||
|
||||
byte = 0x40 +new_data->portid;
|
||||
reg = cmd;
|
||||
outb(byte, ioBase + portid);
|
||||
outb(reg,ioBase + cmdbyte0);
|
||||
byte = 33;
|
||||
outb(byte, ioBase + opcode);
|
||||
addr = addr << 1;
|
||||
addr |= 0x01;
|
||||
outb(addr, ioBase + devaddr);
|
||||
while ((inb(ioBase + ssrr) & 0x40))
|
||||
{
|
||||
/* Wait for the core to be free */
|
||||
pr_debug("CPLD_I2C Wait busy bit(6) to be cleared\n");
|
||||
do {
|
||||
val = inb(ssr);
|
||||
if ((val & CPLD_I2C_BUSY) == 0)
|
||||
break;
|
||||
udelay(100);
|
||||
}
|
||||
} while (true); // Risky - add timeout
|
||||
|
||||
if ((inb(ioBase + ssrr) & 0x80) == 0x80) {
|
||||
/* Read error reset the port */
|
||||
error = -EIO;
|
||||
outb(0x00, ioBase + ssrr);
|
||||
/*
|
||||
* If any error happen here, we do soft-reset
|
||||
* and check the BUSY/ERROR again.
|
||||
*/
|
||||
pr_debug("CPLD_I2C Check error bit(7)\n");
|
||||
if (val & CPLD_I2C_ERR) {
|
||||
pr_debug("CPLD_I2C Error, try soft-reset\n");
|
||||
outb(CPLD_I2C_RESET, ssr);
|
||||
udelay(3000);
|
||||
outb(0x01, ioBase + ssrr);
|
||||
goto exit;
|
||||
outb(CPLD_I2C_UNRESET, ssr);
|
||||
|
||||
val = inb(ssr);
|
||||
if (val & (CPLD_I2C_BUSY | CPLD_I2C_ERR)) {
|
||||
pr_debug("CPLD_I2C Error, core busy after reset\n");
|
||||
error = -EIO;
|
||||
goto exit_unlock;
|
||||
}
|
||||
}
|
||||
|
||||
temp = ioBase + readdata;
|
||||
word_data = inb(temp);
|
||||
word_data |= (inb(++temp) << 8);
|
||||
/* Configure PortID */
|
||||
val = priv->portid | CPLD_I2C_CLK_100Khz_BIT;
|
||||
outb(val, portid);
|
||||
pr_debug("CPLD_I2C Write PortID 0x%x\n", val);
|
||||
|
||||
mutex_unlock(&cpld_data->cpld_lock);
|
||||
data->word = word_data;
|
||||
return 0;
|
||||
/* Configure OP_Code */
|
||||
val = (priv->curr_xfer.data_len << 4) & CPLD_I2C_DATA_SZ_MASK;
|
||||
val |= (priv->curr_xfer.cmd_len & CPLD_I2C_CMD_SZ_MASK);
|
||||
outb(val, opcode);
|
||||
pr_debug("CPLD_I2C Write OP_Code 0x%x\n", val);
|
||||
|
||||
exit:
|
||||
/* Configure CMD_Byte */
|
||||
outb(priv->curr_xfer.cmd[0], cmdbyte0);
|
||||
pr_debug("CPLD_I2C Write CMD_Byte 0x%x\n", priv->curr_xfer.cmd[0]);
|
||||
|
||||
/* Configure write data buffer */
|
||||
if ((priv->curr_xfer.addr & BIT(0)) == I2C_SMBUS_WRITE){
|
||||
pr_debug("CPLD_I2C Write WR_DATA buffer\n");
|
||||
switch(priv->curr_xfer.data_len){
|
||||
case 1:
|
||||
outb(data->byte, writedata);
|
||||
break;
|
||||
case 2:
|
||||
outb(data->block[0], writedata);
|
||||
outb(data->block[1], ++writedata);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
/* Start transfer, write the device address register */
|
||||
pr_debug("CPLD_I2C Write DEV_ADDR 0x%x\n", priv->curr_xfer.addr);
|
||||
outb(priv->curr_xfer.addr, devaddr);
|
||||
|
||||
/* Wait for transfer finish */
|
||||
pr_debug("CPLD_I2C Wait busy bit(6) to be cleared\n");
|
||||
do {
|
||||
val = inb(ssr);
|
||||
if ((val & CPLD_I2C_BUSY) == 0)
|
||||
break;
|
||||
udelay(100);
|
||||
} while (true); // Risky - add timeout
|
||||
|
||||
pr_debug("CPLD_I2C Check error bit(7)\n");
|
||||
if (val & CPLD_I2C_ERR) {
|
||||
error = -EIO;
|
||||
goto exit_unlock;
|
||||
}
|
||||
|
||||
/* Get the data from buffer */
|
||||
if ((priv->curr_xfer.addr & BIT(0)) == I2C_SMBUS_READ){
|
||||
pr_debug("CPLD_I2C Read RD_DATA buffer\n");
|
||||
switch (priv->curr_xfer.data_len) {
|
||||
case 1:
|
||||
data->byte = inb(readdata);
|
||||
break;
|
||||
case 2:
|
||||
data->block[0] = inb(readdata);
|
||||
data->block[1] = inb(++readdata);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
error = 0;
|
||||
|
||||
exit_unlock:
|
||||
pr_debug("CPLD_I2C Exit with %d\n", error);
|
||||
mutex_unlock(&cpld_data->cpld_lock);
|
||||
return error;
|
||||
|
||||
}
|
||||
|
||||
static int dx010_i2c_access(struct i2c_adapter *a, u16 addr,
|
||||
unsigned short flags, char rw, u8 cmd,
|
||||
int size, union i2c_smbus_data *data)
|
||||
{
|
||||
/*
|
||||
* dx010_smbus_xfer - execute LPC-SMBus transfer
|
||||
* Returns a negative errno code else zero on success.
|
||||
*/
|
||||
static s32 dx010_smbus_xfer(struct i2c_adapter *adap, u16 addr,
|
||||
unsigned short flags, char read_write,
|
||||
u8 command, int size, union i2c_smbus_data *data) {
|
||||
|
||||
int error = 0;
|
||||
struct dx010_i2c_data *priv;
|
||||
|
||||
struct dx010_i2c_data *new_data;
|
||||
priv = i2c_get_adapdata(adap);
|
||||
|
||||
/* Write the command register */
|
||||
new_data = i2c_get_adapdata(a);
|
||||
pr_debug("smbus_xfer called RW:%x CMD:%x SIZE:0x%x",
|
||||
read_write, command, size);
|
||||
|
||||
priv->curr_xfer.addr = (addr << 1) | read_write;
|
||||
priv->curr_xfer.data = data;
|
||||
|
||||
/* Map the size to what the chip understands */
|
||||
switch (size) {
|
||||
case I2C_SMBUS_QUICK:
|
||||
size = HST_CNTL2_QUICK;
|
||||
break;
|
||||
case I2C_SMBUS_BYTE:
|
||||
size = HST_CNTL2_BYTE;
|
||||
break;
|
||||
priv->curr_xfer.cmd_len = 0;
|
||||
priv->curr_xfer.data_len = 1;
|
||||
break;
|
||||
case I2C_SMBUS_BYTE_DATA:
|
||||
size = HST_CNTL2_BYTE_DATA;
|
||||
break;
|
||||
priv->curr_xfer.cmd_len = 1;
|
||||
priv->curr_xfer.data_len = 1;
|
||||
priv->curr_xfer.cmd[0] = command;
|
||||
break;
|
||||
case I2C_SMBUS_WORD_DATA:
|
||||
size = HST_CNTL2_WORD_DATA;
|
||||
break;
|
||||
case I2C_SMBUS_BLOCK_DATA:
|
||||
size = HST_CNTL2_BLOCK;
|
||||
break;
|
||||
priv->curr_xfer.cmd_len = 1;
|
||||
priv->curr_xfer.data_len = 2;
|
||||
priv->curr_xfer.cmd[0] = command;
|
||||
break;
|
||||
default:
|
||||
dev_warn(&a->dev, "Unsupported transaction %d\n", size);
|
||||
dev_warn(&adap->dev, "Unsupported transaction %d\n", size);
|
||||
error = -EOPNOTSUPP;
|
||||
goto Done;
|
||||
}
|
||||
|
||||
switch (size) {
|
||||
case HST_CNTL2_BYTE: /* Result put in SMBHSTDAT0 */
|
||||
break;
|
||||
case HST_CNTL2_BYTE_DATA:
|
||||
break;
|
||||
case HST_CNTL2_WORD_DATA:
|
||||
if( 0 == i2c_read_eeprom(a,addr,new_data,cmd,data)){
|
||||
error = 0;
|
||||
}else{
|
||||
error = -EIO;
|
||||
}
|
||||
break;
|
||||
}
|
||||
error = cpld_smbus_transfer(priv);
|
||||
|
||||
Done:
|
||||
return error;
|
||||
}
|
||||
|
||||
static u32 dx010_i2c_func(struct i2c_adapter *a)
|
||||
{
|
||||
return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
|
||||
I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
|
||||
I2C_FUNC_SMBUS_BLOCK_DATA;
|
||||
// TODO: Add support for I2C_FUNC_SMBUS_PROC_CALL and I2C_FUNC_SMBUS_I2C_BLOCK
|
||||
static u32 dx010_i2c_func(struct i2c_adapter *a) {
|
||||
return I2C_FUNC_SMBUS_READ_BYTE |
|
||||
I2C_FUNC_SMBUS_BYTE_DATA |
|
||||
I2C_FUNC_SMBUS_WORD_DATA;
|
||||
}
|
||||
|
||||
static const struct i2c_algorithm dx010_i2c_algorithm = {
|
||||
.smbus_xfer = dx010_i2c_access,
|
||||
.smbus_xfer = dx010_smbus_xfer,
|
||||
.functionality = dx010_i2c_func,
|
||||
};
|
||||
|
||||
static struct i2c_adapter * cel_dx010_i2c_init(struct platform_device *pdev, int portid)
|
||||
static struct i2c_adapter *cel_dx010_i2c_init(struct platform_device *pdev, int portid)
|
||||
{
|
||||
int error;
|
||||
|
||||
int base_addr;
|
||||
struct i2c_adapter *new_adapter;
|
||||
struct dx010_i2c_data *new_data;
|
||||
struct dx010_i2c_data *priv;
|
||||
|
||||
switch (portid) {
|
||||
case PORT_SFPP1 ... PORT_SFPP2:
|
||||
case PORT_BANK1_START ... PORT_BANK1_END:
|
||||
base_addr = CPLD_I2C_BANK1_BASE;
|
||||
break;
|
||||
case PORT_BANK2_START ... PORT_BANK2_END:
|
||||
base_addr = CPLD_I2C_BANK2_BASE;
|
||||
break;
|
||||
case PORT_BANK3_START ... PORT_BANK3_END:
|
||||
base_addr = CPLD_I2C_BANK3_BASE;
|
||||
break;
|
||||
default:
|
||||
dev_err(&pdev->dev, "Invalid port adapter ID: %d\n", portid);
|
||||
goto error_exit;
|
||||
}
|
||||
|
||||
new_adapter = kzalloc(sizeof(*new_adapter), GFP_KERNEL);
|
||||
if (!new_adapter)
|
||||
@ -544,31 +585,39 @@ static struct i2c_adapter * cel_dx010_i2c_init(struct platform_device *pdev, int
|
||||
|
||||
new_adapter->dev.parent = &pdev->dev;
|
||||
new_adapter->owner = THIS_MODULE;
|
||||
new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
|
||||
new_adapter->class = I2C_CLASS_DEPRECATED;
|
||||
new_adapter->algo = &dx010_i2c_algorithm;
|
||||
|
||||
snprintf(new_adapter->name, sizeof(new_adapter->name),
|
||||
"SMBus dx010 i2c Adapter portid@%04x", portid);
|
||||
"SMBus dx010 i2c Adapter port %d", portid);
|
||||
|
||||
new_data = kzalloc(sizeof(*new_data), GFP_KERNEL);
|
||||
if (!new_data)
|
||||
return NULL;
|
||||
priv = kzalloc(sizeof(*priv), GFP_KERNEL);
|
||||
if (!priv) {
|
||||
goto free_adap;
|
||||
}
|
||||
|
||||
new_data->portid = portid;
|
||||
|
||||
i2c_set_adapdata(new_adapter,new_data);
|
||||
priv->portid = portid;
|
||||
priv->base_addr = base_addr;
|
||||
|
||||
i2c_set_adapdata(new_adapter, priv);
|
||||
error = i2c_add_adapter(new_adapter);
|
||||
if(error)
|
||||
return NULL;
|
||||
goto free_data;
|
||||
|
||||
return new_adapter;
|
||||
|
||||
free_adap:
|
||||
kzfree(new_adapter);
|
||||
free_data:
|
||||
kzfree(priv);
|
||||
error_exit:
|
||||
return NULL;
|
||||
};
|
||||
|
||||
static int cel_dx010_lpc_drv_probe(struct platform_device *pdev)
|
||||
{
|
||||
struct resource *res;
|
||||
int ret =0;
|
||||
int ret = 0;
|
||||
int portid_count;
|
||||
|
||||
cpld_data = devm_kzalloc(&pdev->dev, sizeof(struct dx010_cpld_data),
|
||||
|
||||
@ -0,0 +1,75 @@
|
||||
#!/bin/bash
|
||||
#
|
||||
# Copyright 2020-present Celestica. All Rights Reserved.
|
||||
#
|
||||
# This program file is free software; you can redistribute it and/or modify it
|
||||
# under the terms of the GNU General Public License as published by the
|
||||
# Free Software Foundation; version 2 of the License.
|
||||
#
|
||||
# This program is distributed in the hope that it will be useful, but WITHOUT
|
||||
# ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
|
||||
# FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
|
||||
# for more details.
|
||||
#
|
||||
#
|
||||
|
||||
PATH=/sbin:/bin:/usr/sbin:/usr/bin:/usr/local/bin
|
||||
SETREG_FILE=/sys/devices/platform/dx010_cpld/setreg
|
||||
TOVERREG=0x140
|
||||
CPUOVER=0xa1
|
||||
ASICOVER=0xa2
|
||||
|
||||
prog="$0"
|
||||
command="$1"
|
||||
|
||||
if [[ $EUID -ne 0 ]]; then
|
||||
echo "This script must be run as root"
|
||||
exit 1
|
||||
fi
|
||||
|
||||
usage() {
|
||||
echo "Usage: thermal_overload_control.sh [option] <command>"
|
||||
echo
|
||||
echo "Options:"
|
||||
echo " -h, --help : to print this message."
|
||||
echo
|
||||
echo "Commands:"
|
||||
echo
|
||||
echo " cpu: To enabling CPU thermal overload handler"
|
||||
echo
|
||||
echo " asic : To enabling ASIC thermal overload handler"
|
||||
echo
|
||||
}
|
||||
|
||||
cpu_overload() {
|
||||
logger "Enable CPU thermal overload control"
|
||||
set_reg=`echo ${TOVERREG} ${CPUOVER} > ${SETREG_FILE}`
|
||||
}
|
||||
|
||||
asic_overload() {
|
||||
logger "Enable ASIC thermal overload control"
|
||||
set_reg=`echo ${TOVERREG} ${ASICOVER} > ${SETREG_FILE}`
|
||||
}
|
||||
|
||||
if [ $# -lt 1 ]; then
|
||||
usage
|
||||
exit -1
|
||||
fi
|
||||
|
||||
case "$command" in
|
||||
-h | --help)
|
||||
usage
|
||||
;;
|
||||
cpu)
|
||||
cpu_overload
|
||||
;;
|
||||
asic)
|
||||
asic_overload
|
||||
;;
|
||||
*)
|
||||
usage
|
||||
exit -1
|
||||
;;
|
||||
esac
|
||||
|
||||
exit $?
|
||||
File diff suppressed because it is too large
Load Diff
Loading…
Reference in New Issue
Block a user