- Enable thermalctld support for our platforms
- Fix Chassis.get_num_sfp which had an off by one
- Implement read_eeprom and write_eeprom in SfpBase
- Refactor of Psus and PsuSlots. Psus they are now detected and metadata reported
- Improvements to modular support
Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
bring up chassisdb service on sonic switch according to the design in
Distributed Forwarding in VoQ Arch HLD
Signed-off-by: Honggang Xu <hxu@arista.com>
**- Why I did it**
To bring up new ChassisDB service in sonic as designed in ['Distributed forwarding in a VOQ architecture HLD' ](90c1289eaf/doc/chassis/architecture.md).
**- How I did it**
Implement the section 2.3.1 Global DB Organization of the VOQ architecture HLD.
**- How to verify it**
ChassisDB service won't start without chassisdb.conf file on the existing platforms.
ChassisDB service is accessible with global.conf file in the distributed arichitecture.
Signed-off-by: Honggang Xu <hxu@arista.com>
This is to fix pcie firmware check assert in Broadcom SDK once the SAI changes merges. This will be in the future but adding the soc property in the broadcom config now.
Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
However in SAI 3.7 default behaviout got changes to 128 Group and 128
Memeber each.
This change is to make sure we are using same ECMP Group/Memeber Per
Group for 3.7 also so that behaviour is consistent.
Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
- Merge chassis codebase upstream
- Add support for Otterlake supervisor
- Add support for NorthFace and Camp chassis
- Add support for Eldridge, Dragonfly and Brooks fabrics
- Add support for Clearwater2 and Clearwater2Ms linecards
- Add new arista Cli to power on/off cards
- Add new arista show Cli to inspect supervisor, chassis, fabrics and linecards
as needed by SAI 3.7 and above. Without this change
Warmboot fails from 3.5 to 3.7 as Braodcoam Datastructure
gets corrupted after warm-boot.
Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
thermalctld throwing error messages because it is not yet fully configured, disabling it for now on arista platforms.
Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
- Sensor and Fan information added to primary platforms for thermal API.
- Refactors involving better abstractions, code reuse and dead code removal.
- Improvements to the diag capabilities
- Pylintrc added to improve code quality. Will become fatal at a later time.
Co-authored-by: Baptiste Covolato <baptiste@arista.com>
Dynamic threshold setting changed to 0 and WRED profile green min threshold set to 250000 for Tomahawk devices
Changed the dynamic threshold settings in pg_profile_lookup.ini
Added a macro for WRED profiles in qos.json.j2 for Tomahawk devices
Necessary changes made in qos.config.j2 to use the macro if present
Signed-off-by: Neetha John <nejo@microsoft.com>
* Update arista driver submodule
* Add support for 7260CX3-64E in boot0
* Refactor boot0 platform specific definition
Make it easier to manage new sku
* Add support for 7050CX3-32S in boot0
Just contains the required boot0 information
* Add basic plugin support for DCS-7050CX3-32S
* Add port config for Arista-7050CX3-32S-C32
Co-authored-by: yurypm <yurypm@arista.com>
Co-authored-by: byu343 <byu@arista.com>
* Remove the divide by 4 operation to the under the hood SAI
This is to avoid the need and thus the confusion for application program to know
the mmu internal architecture
This change must have support from SAI change to reach the correct
config
Signed-off-by: Wenda <wenni@microsoft.com>
* Relegate the divide by 4 operation to the under the hood SAI for egress
lossless pool
Extend to 7060 and 6100
Signed-off-by: Wenda <wenni@microsoft.com>
* Add more TH/TH2 hwskus
Signed-off-by: Wenda Ni <wenni@microsoft.com>
* Update config test
Signed-off-by: Wenda Ni <wenni@microsoft.com>
* Add TH2 ingress lossy profile
Signed-off-by: Wenda Ni <wenni@microsoft.com>
* Move the divide by 4 operation to SAI internal
Signed-off-by: Wenda Ni <wenni@microsoft.com>
* [bcm SAI] Upgrade Broadcom SAI to version 3.5.3.1-15
- Broadcom SAI 3.5 GA release 20190924.
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
* Add boot0 support for the 7280CR3
* Add platform and plugins for 7280CR3
* Add port config for 7280CR3
* Add platform_reboot for 7280CR3
* Add support for 7280CR3-32D4 based on the 7280CR3-32P4
* Update arista driver submodules
- Introduce new 7280CR3-32P4
- Improve to the led plugin for OSFP
* Fix showing systemd shutdown sequence when verbose is set
* Fix creation of kernel-cmdline file
Sometimes boot0 prints error
"mv: can't preserve ownership of '/mnt/flash/image-arsonic.xxxx/kernel-cmdline': Operation not permitted"
* Improve flash space usage during installation
Some older systems only have 2GB of flash available. Installing a second
image on these can prove to be challenging.
The new installation process moves the installer swi to memory in order
to avoid free up space from the flash before uncompressing it there.
It removes all the flash space usage spike and also improves the IO
since the installation is no more reading and writting to the flash at
the same time.
* Add support of 7060CX-32S-SSD
* 7260CX3: use inventory powerCycle procedures
* 7050QX-32S: use inventory powerCycle procedures
* 7050QX-32: use inventory powerCycle procedures
* platform: arista: add common platform_reboot
Replace platform_reboot by a link to new common for devices already
using a similar script.
* 7060CX-32S: use inventory powerCycle procedures
* Install python smbus in pmon
Some platform plugin need the python smbus library to perform some actions.
This installs the dependency.
* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU
Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines
Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
* [HWSKU] Added Arista-7060CX-32S-T96C8 HWSKU
Added the bcm config files for a 96x25G+8x100G ToR
Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU
Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines
Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
* QoS config change: 1) DSCP mapping; 2) link pg/queue 6 to lossy buffer;
3) redistribute scheduler
Signed-off-by: Wenda <wenni@microsoft.com>
* Add scheduling weight to queue 2
Signed-off-by: Wenda <wenni@microsoft.com>
* Link pg/queue 2 to lossy buffer
Signed-off-by: Wenda <wenni@microsoft.com>
* Update the pg headroom for a7060-D48C8 50G
Signed-off-by: Wenda <wenni@microsoft.com>
* Update config gen test for qos
Signed-off-by: Wenda <wenni@microsoft.com>
* Update pg headroom size, and update egress lossy pool size accordingly
Signed-off-by: Wenda <wenni@microsoft.com>
* Update headroom pool size; Update ingress service pool and egress lossy
pool sizes accordingly;
Signed-off-by: Wenda <wenni@microsoft.com>
* a7260: update headroom pool size; Update ingress service pool and egress lossy pool sizes accordingly;
Signed-off-by: Wenda <wenni@microsoft.com>
* Update config gen test for buffer
Signed-off-by: Wenda <wenni@microsoft.com>
* 1) DSCP 46 to 5; 2) ecn config for lossless traffic; 3) ecn on by default; 4) DWRR equal weight;
Signed-off-by: Wenda <wenni@microsoft.com>
* 1) link pg & queue 5 to lossy buffer profile; 2) ingress lossless alpha 1/8
Signed-off-by: Wenda <wenni@microsoft.com>
* Update the test case for qos & buffer json template
Signed-off-by: Wenda <wenni@microsoft.com>
* Migrate a7050-qx32 and s6000 to use pg_profile lookup architecture
Signed-off-by: Wenda <wenni@microsoft.com>
* Update pg headroom egress service pool for a7050-qx-32s, a7050-qx32, and s6000
Signed-off-by: Wenda <wenni@microsoft.com>
* Link queue 5 to lossy profile
Signed-off-by: Wenda <wenni@microsoft.com>
