sonic-buildimage/device/celestica
Ikki Zhu db12b8c9c0
dx010 fix possible cpld race read issue (#15339)
#### Why I did it
fix possible cpld race read issue between watchdog and reboot cause process

##### Work item tracking
- Microsoft ADO **(number only)**:

#### How I did it
Use flock to limit parallel access to cpld sys file

#### How to verify it
It can be simulate and verified with following python script

```python3
import signal
import subprocess
import threading

exit_flag = False

def run_command(cmd):
    status = True
    result = ""
    try:
        p = subprocess.Popen(
            cmd, shell=True, universal_newlines=True,
stdout=subprocess.PIPE, stderr=subprocess.PIPE)
        raw_data, err = p.communicate()
        if err == '':
            result = raw_data.strip()
    except:
        status = False
    return status, result

def get_cpld_reg_value(getreg_path, register):
    #cmd = "echo {1} > {0}; cat {0}".format(getreg_path, register)
    cmd = "flock {0} -c 'echo {1} > {0}; cat {0}'".format(getreg_path,
register)
    status, result = run_command(cmd)
    return result if status else None

def cpld_read(thread_num, cpld_reg):
    while not exit_flag:
        val
= get_cpld_reg_value("/sys/devices/platform/dx010_cpld/getreg",
cpld_reg)
        print(f"Thread {thread_num}: get cpld reg {cpld_reg}, value
{val}")

def signal_handler(sig, frame):
    global exit_flag
    print("Ctrl+C detected. Quitting...")
    exit_flag = True

if __name__ == '__main__':
    # Register the signal handler for Ctrl+C
    signal.signal(signal.SIGINT, signal_handler)

    t1 = threading.Thread(target=cpld_read, args=(1, '0x103',))
    t2 = threading.Thread(target=cpld_read, args=(2, '0x141',))
    t1.start()
    t2.start()
    t1.join()
    t2.join()
```
2023-06-20 16:21:08 -07:00
..
x86_64-cel_e1031-r0 [hlx/sfp] fix hlx platform sfp+ tx disable issue (#11532) 2022-08-09 21:05:08 +00:00
x86_64-cel_midstone-r0 [sonic-utilities] Update submodule; Build and install as a Python 3 wheel (#5926) 2020-11-25 10:28:36 -08:00
x86_64-cel_seastone_2-r0 [Celestica/Seastone2] Load interface LEDs (#9769) 2022-01-25 22:17:40 +00:00
x86_64-cel_seastone-r0 dx010 fix possible cpld race read issue (#15339) 2023-06-20 16:21:08 -07:00
x86_64-cel_silverstone-r0 [202012][BRCM TH3] Add SOC properties to prevent FDB events during warmboot (#9761) 2022-01-14 14:44:43 -08:00