[202012][BRCM TH3] Add SOC properties to prevent FDB events during warmboot (#9761)

device/accton/x86_64-accton_as9716_32d-r0/Accton-AS9716-32D/th3-as9716-32x400G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 pbmp_xport_xe.0=0x3ffffffffffffffffffffffffffffffffffffffe
 
 # Reference specfic

device/arista/x86_64-arista_7060dx4_32/Arista-7060DX4-C32/th3-a7060dx4-c32-32x400G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 arl_clean_timeout_usec=15000000
 asf_mem_profile.0=2
 bcm_num_cos.0=8

device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-C64/th3-a7060px4-32-64x100G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 # Disable Counting ACL Drop towards interface RX_DRP counter
 sai_adjust_acl_drop_in_rx_drop=1
 # disables bcmALPMDH (ALPM distributed hitbit) thread.  This thread is purely for debug purpose

device/arista/x86_64-arista_7060px4_32/Arista-7060PX4-O32/th3-a7060px4-o32-32x400G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 # Disable Counting ACL Drop towards interface RX_DRP counter
 sai_adjust_acl_drop_in_rx_drop=1
 # disables bcmALPMDH (ALPM distributed hitbit) thread.  This thread is purely for debug purpose

device/celestica/x86_64-cel_silverstone-r0/Silverstone-128x100/th3-128x100G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 pbmp_xport_xe.0=0x8ffff8ffffcffff8ffff8ffff8ffffcffff9fffe
 ccm_dma_enable=0
 ccmdma_intr_enable=0

device/celestica/x86_64-cel_silverstone-r0/Silverstone/th3-32x400G.config.bcm

@@ -1,3 +1,6 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
 
 pbmp_xport_xe.0=0x8111181111c1111811118111181111c111182222
 ccm_dma_enable=0

device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-C32/th3-z9332f-32x100G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 sai_tunnel_global_sip_mask_enable=1
 core_clock_frequency=1325
 dpr_clock_frequency=1000

device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-M-O16C64/th3-z9332f-16x400G-64x100G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 sai_tunnel_global_sip_mask_enable=1
 core_clock_frequency=1325
 dpr_clock_frequency=1000

device/dell/x86_64-dellemc_z9332f_d1508-r0/DellEMC-Z9332f-O32/th3-z9332f-32x400G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 sai_tunnel_global_sip_mask_enable=1
 core_clock_frequency=1325
 dpr_clock_frequency=1000

device/delta/x86_64-delta_agc032-r0/Delta-agc032/th3-agc032-32x400G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 #########################################
 ## cfg for AGC032
 #########################################

device/quanta/x86_64-quanta_ix9_bwde-r0/Quanta-IX9-32X/th3-ix9-32x400G.config.bcm

@@ -1,3 +1,7 @@
+# The following 2 SOC properties are needed to prevent FDB Events during Warmboot due to TH3 is SW Managed MACs
+l2xmsg_shadow_hit_bits=0
+l2xmsg_no_cb_during_table_rebuild=1
+
 phy_null=1
 pll_bypass=1
 

src/sonic-device-data/tests/permitted_list

@@ -239,3 +239,5 @@ buf.map.egress_pool2.ingress_pool
 sai_adjust_acl_drop_in_rx_drop
 sai_verify_incoming_chksum
 l3_alpm_hit_skip
+l2xmsg_shadow_hit_bits
+l2xmsg_no_cb_during_table_rebuild