sonic-buildimage/device/arista/x86_64-arista_7260cx3_64
bingwang-ms d9cd1a1355 Add extra lossy PG profile for ports between T1 and T2 (#11157)
Signed-off-by: bingwang <wang.bing@microsoft.com>

Why I did it
This PR brings two changes

Add lossy PG profile for PG2 and PG6 on T1 for ports between T1 and T2.
After PR Update qos config to clear queues for bounced back traffic #10176 , the DSCP_TO_TC_MAP and TC_TO_PG_MAP is updated when remapping is enable

DSCP_TO_TC_MAP
Before	After	Why do this change
"2" : "1"	"2" : "2"	Only change for leaf router to map DSCP 2 to TC 2 as TC 2 will be used for lossless TC
"6" : "1"	"6" : "6"	Only change for leaf router to map DSCP 6 to TC 6 as TC 6 will be used for lossless TC

TC_TO_PRIORITY_GROUP_MAP
Before	After	Why do this change
"2" : "0"	"2" : "2"	Only change for leaf router to map TC 2 to PG 2 as PG 2 will be used for lossless PG
"6" : "0"	"6" : "6"	Only change for leaf router to map TC 6 to PG 6 as PG 6 will be used for lossless PG

So, we have two new lossy PGs (2 and 6) for the T2 facing ports on T1, and two new lossless PGs (2 and 6) for the T0 facing port on T1.
However, there is no lossy PG profile for the T2 facing ports on T1. The lossless PGs for ports between T1 and T0 have been handled by buffermgrd .Therefore, We need to add lossy PG profiles for T2 facing ports on T1.

We don't have this issue on T0 because PG 2 and PG 6 are lossless PGs, and there is no lossy traffic mapped to PG 2 and PG 6

Map port level TC7 to PG0
Before the PCBB change, DSCP48 -> TC 6 -> PG 0.
After the PCBB change, DSCP48 -> TC 7 -> PG 7
Actually, we can map TC7 to PG0 to save a lossy PG.

How I did it
Update the qos and buffer template.

How to verify it
Verified by UT.
2022-06-30 05:15:41 +00:00
..
Arista-7260CX3-64 [Arista] Add dynamic port breakout hwsku to platforms (#7975) 2021-08-16 07:03:50 -07:00
Arista-7260CX3-C64 Add extra lossy PG profile for ports between T1 and T2 (#11157) 2022-06-30 05:15:41 +00:00
Arista-7260CX3-D108C8 [qos]: Adjust 7260 buffer sizes to accomodate extra lossless queues (#11018) 2022-06-23 02:33:48 +00:00
Arista-7260CX3-Q64 Add extra lossy PG profile for ports between T1 and T2 (#11157) 2022-06-30 05:15:41 +00:00
plugins [pcie.yaml] Move pcie configuration file path to platform directory (#6475) 2021-02-21 08:27:37 -08:00
Arista-7260CX3-Q44 [HWSKU] Define HWSKU Arista-7260CX3-Q64 and Arista-7260CX3-Q44 (#2562) 2019-02-14 11:27:15 -08:00
default_sku [updategraph] add support to use preset config instead of default minigraph (#2050) 2018-09-21 22:01:10 -07:00
fancontrol [devices]: Add device data for Arista 7060PX/DX4-32 (#2534) 2019-02-08 22:02:01 -08:00
pcie.yaml [pcie.yaml] Move pcie configuration file path to platform directory (#6475) 2021-02-21 08:27:37 -08:00
platform_asic Add platform_asic file to each platform folder in sonic-device-data based package (#8542) 2021-10-08 19:27:48 -07:00
platform_reboot [device/Arista] Improvements to the boot of Arista devices. (#2898) 2019-05-15 12:45:05 -07:00
platform.json [Arista] Add dynamic port breakout hwsku to platforms (#7975) 2021-08-16 07:03:50 -07:00
pmon_daemon_control.json [Arista] Update driver submodules (#5686) 2020-10-23 12:28:36 -07:00
sensors.conf [arista]: Unify labels for Arista sensors (#1216) 2017-12-08 12:01:06 -08:00
system_health_monitoring_config.json [arista]: Add placeholder healthd configuration for all platforms (#6233) 2020-12-17 05:18:38 -08:00
th2-a7260cx3-64-flex.config.bcm [Arista] Add dynamic port breakout hwsku to platforms (#7975) 2021-08-16 07:03:50 -07:00
thermal_policy.json [Arista] Update driver submodules (#5686) 2020-10-23 12:28:36 -07:00