sonic-buildimage/device/arista/x86_64-arista_7050cx3_32s/Arista-7050CX3-32S-D48C8
Dev Ojha 648ddee39c [Arista7050cx3] TD3 SKU changes for pg headroom value after interop testing with cisco 8102 (#11901)
Why I did it
After PFC interop testing between 8102 and 7050cx3, data packet losses were observed on the Rx ports of the 7050cx3 (inflow from 8102) during testing. This was primarily due to the slower response times to react to PFC pause packets for the 8102, when receiving such frames from neighboring devices. To solve for the packet drops, the 7050cx3 pg headroom size has to be increased to 160kB.

How I did it
Modified the xoff threshold value to 160kB in the pg_profile file to allow for the buffer manager to read that value when building the image, and configuring the device

How to verify it
run "mmuconfig -l" once image is built


Signed-off-by: dojha <devojha@microsoft.com>
2022-09-01 00:13:15 +00:00
..
buffers_defaults_t0.j2 Updated buffer profile settings for TD3 based HWSKUs (Arista-7050CX3-32S-C32, Arista-7050CX3-32S-D48C8) (#11202) 2022-06-24 05:15:14 +00:00
buffers_extra_queues.j2 Add two extra lossless queues for bounced back traffic (#10496) 2022-06-22 23:05:14 +00:00
buffers.json.j2 Updated Qos/MMU settings for Arista-7050CX3-32S-C32 & Arista-7050CX3-32S-D48C8 (#7068) 2021-04-30 10:02:08 -07:00
config.bcm.j2 [device]: Add SAI checksum verify to TD3 config (#8857) 2022-07-17 03:11:54 +00:00
pg_profile_lookup.ini [Arista7050cx3] TD3 SKU changes for pg headroom value after interop testing with cisco 8102 (#11901) 2022-09-01 00:13:15 +00:00
port_config.ini [arista]: Add new 48x50G + 8x100G hwsku for Lodoga (#5452) 2020-09-23 22:41:07 -07:00
qos.json.j2 Add extra lossy PG profile for ports between T1 and T2 (#11157) 2022-06-30 05:15:41 +00:00
sai.profile [Tunnel PFC] Add property for tunnel PFC (#10962) 2022-06-05 15:21:24 +00:00