1acafa4873
Why I did it Add PDDF support on following Ufispace platforms with Broadcom ASIC S9110-32X S8901-54XC S7801-54XS S6301-56ST How I did it Add PDDF configuration files, scripts and python files How to verify it Run pddf commands and show commands. Signed-off-by: nonodark <ef67891@yahoo.com.tw>
270 lines
10 KiB
C
270 lines
10 KiB
C
/* header file for i2c cpld driver of ufispace_s8901_54xc
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*
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* Copyright (C) 2022 UfiSpace Technology Corporation.
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* Jason Tsai <jason.cy.tsai@ufispace.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef UFISPACE_S8901_54XC_CPLD_H
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#define UFISPACE_S8901_54XC_CPLD_H
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/* CPLD device index value */
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enum cpld_id {
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cpld1,
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cpld2
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};
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/* CPLD common registers */
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#define CPLD_VERSION_REG 0x02
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#define CPLD_ID_REG 0x03
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#define CPLD_BUILD_REG 0x04
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#define CPLD_CHIP_REG 0x05
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#define CPLD_EVT_CTRL_REG 0x3F
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/* CPLD 1 registers */
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#define CPLD_BOARD_ID_0_REG 0x00
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#define CPLD_BOARD_ID_1_REG 0x01
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#define CPLD_SKU_EXT_REG 0x06
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#define CPLD_MAC_INTR_REG 0x10
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#define CPLD_HWM_INTR_REG 0x13
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#define CPLD_CPLD2_INTR_REG 0x14
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#define CPLD_NTM_INTR_REG 0x15
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#define CPLD_FAN_PSU_INTR_REG 0x16
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#define CPLD_SFP_IOEXP_INTR_REG 0x18
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#define CPLD_CPU_NMI_INTR_REG 0x19
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#define CPLD_PTP_INTR_REG 0x1B
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#define CPLD_SYSTEM_INTR_REG 0x1C
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#define CPLD_MAC_MASK_REG 0x20
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#define CPLD_HWM_MASK_REG 0x23
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#define CPLD_CPLD2_MASK_REG 0x24
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#define CPLD_NTM_MASK_REG 0x25
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#define CPLD_FAN_PSU_MASK_REG 0x26
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#define CPLD_SFP_IOEXP_MASK_REG 0x28
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#define CPLD_CPU_NMI_MASK_REG 0x29
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#define CPLD_PTP_MASK_REG 0x2B
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#define CPLD_SYSTEM_MASK_REG 0x2C
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#define CPLD_MAC_EVT_REG 0x30
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#define CPLD_HWM_EVT_REG 0x33
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#define CPLD_CPLD2_EVT_REG 0x34
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#define CPLD_NTM_EVT_REG 0x35
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#define CPLD_FAN_PSU_EVT_REG 0x36
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#define CPLD_SFP_IOEXP_EVT_REG 0x38
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#define CPLD_CPU_NMI_EVT_REG 0x39
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#define CPLD_PTP_EVT_REG 0x3B
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#define CPLD_MAC_RESET_REG 0x40
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#define CPLD_SYSTEM_RESET_REG 0x41
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#define CPLD_BMC_NTM_RESET_REG 0x43
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#define CPLD_USB_RESET_REG 0x44
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#define CPLD_I2C_MUX_RESET_REG 0x46
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#define CPLD_I2C_MUX_RESET_2_REG 0x47
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#define CPLD_MISC_RESET_REG 0x48
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#define CPLD_BRD_PRESENT_REG 0x50
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#define CPLD_PSU_STATUS_REG 0x51
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#define CPLD_SYSTEM_PWR_REG 0x52
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#define CPLD_MAC_SYNCE_REG 0x53
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#define CPLD_MAC_AVS_REG 0x54
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#define CPLD_SYSTEM_STATUS_REG 0x55
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#define CPLD_FAN_PRESENT_REG 0x56
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#define CPLD_WATCHDOG_REG 0x5A
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#define CPLD_BOOT_SELECT_REG 0x5B
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#define CPLD_MUX_CTRL_REG 0x5C
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#define CPLD_MISC_CTRL_1_REG 0x5D
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#define CPLD_MISC_CTRL_2_REG 0x5E
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#define CPLD_TIMING_CTRL_REG 0x5F
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#define CPLD_MAC_TEMP_REG 0x61
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/*
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#define CPLD_SYSTEM_LED_SYS_FAN_REG 0x80
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#define CPLD_SYSTEM_LED_PSU_REG 0x81
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#define CPLD_SYSTEM_LED_SYNC_REG 0x82
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#define CPLD_SYSTEM_LED_ID_REG 0x84
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*/
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#define CPLD_SYSTEM_LED_PSU_REG 0x80
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#define CPLD_SYSTEM_LED_SYS_REG 0x81
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#define CPLD_SYSTEM_LED_SYNC_REG 0x82
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#define CPLD_SYSTEM_LED_FAN_REG 0x83
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#define CPLD_SYSTEM_LED_ID_REG 0x84
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#define CPLD_MAC_PG_REG 0x90
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#define CPLD_MISC_PG_REG 0x92
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#define CPLD_MAC_PG_EN_REG 0x93
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#define CPLD_MISC_PG_EN_REG 0x95
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#define DBG_CPLD_MAC_INTR_REG 0xE0
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#define DBG_CPLD_HWM_INTR_REG 0xE3
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#define DBG_CPLD_CPLD2_INTR_REG 0xE4
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#define DBG_CPLD_NTM_INTR_REG 0xE5
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#define DBG_CPLD_FAN_PSU_INTR_REG 0xE6
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#define DBG_CPLD_SFP_IOEXP_INTR_REG 0xE8
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#define DBG_CPLD_PTP_INTR_REG 0xEB
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#define CPLD_UPG_RESET_REG 0xF0
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/* CPLD 2*/
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//interrupt status
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#define CPLD_SFP_INTR_PRESENT_0_7_REG 0x10
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#define CPLD_SFP_INTR_PRESENT_8_15_REG 0x11
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#define CPLD_SFP_INTR_PRESENT_16_23_REG 0x12
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#define CPLD_SFP_INTR_PRESENT_24_31_REG 0x13
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#define CPLD_SFP_INTR_PRESENT_32_39_REG 0x14
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#define CPLD_SFP_INTR_PRESENT_40_47_REG 0x15
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#define CPLD_QSFP_INTR_PRESENT_48_53_REG 0x16
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#define CPLD_QSFP_INTR_PORT_48_53_REG 0x17
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//interrupt mask
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#define CPLD_SFP_MASK_PRESENT_0_7_REG 0x20
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#define CPLD_SFP_MASK_PRESENT_8_15_REG 0x21
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#define CPLD_SFP_MASK_PRESENT_16_23_REG 0x22
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#define CPLD_SFP_MASK_PRESENT_24_31_REG 0x23
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#define CPLD_SFP_MASK_PRESENT_32_39_REG 0x24
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#define CPLD_SFP_MASK_PRESENT_40_47_REG 0x25
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#define CPLD_QSFP_MASK_PRESENT_48_53_REG 0x26
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#define CPLD_QSFP_MASK_PORT_48_53_REG 0x27
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//interrupt event
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#define CPLD_SFP_EVT_PRESENT_0_7_REG 0x30
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#define CPLD_SFP_EVT_PRESENT_8_15_REG 0x31
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#define CPLD_SFP_EVT_PRESENT_16_23_REG 0x32
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#define CPLD_SFP_EVT_PRESENT_24_31_REG 0x33
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#define CPLD_SFP_EVT_PRESENT_32_39_REG 0x34
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#define CPLD_SFP_EVT_PRESENT_40_47_REG 0x35
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#define CPLD_QSFP_EVT_PRESENT_48_53_REG 0x36
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#define CPLD_QSFP_EVT_PORT_48_53_REG 0x37
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#define CPLD_SFP_INTR_RX_LOS_0_7_REG 0x40
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#define CPLD_SFP_INTR_RX_LOS_8_15_REG 0x41
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#define CPLD_SFP_INTR_RX_LOS_16_23_REG 0x42
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#define CPLD_SFP_INTR_RX_LOS_24_31_REG 0x43
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#define CPLD_SFP_INTR_RX_LOS_32_39_REG 0x44
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#define CPLD_SFP_INTR_RX_LOS_40_47_REG 0x45
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#define CPLD_SFP_INTR_TX_FAULT_0_7_REG 0x46
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#define CPLD_SFP_INTR_TX_FAULT_8_15_REG 0x47
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#define CPLD_SFP_INTR_TX_FAULT_16_23_REG 0x48
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#define CPLD_SFP_INTR_TX_FAULT_24_31_REG 0x49
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#define CPLD_SFP_INTR_TX_FAULT_32_39_REG 0x4A
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#define CPLD_SFP_INTR_TX_FAULT_40_47_REG 0x4B
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//#define CPLD_SFP_RX_LOS_BASE_REG 0x40
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//#define CPLD_SFP_TX_FAULT_BASE_REG 0x46
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#define CPLD_SFP_MASK_RX_LOS_0_7_REG 0x50
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#define CPLD_SFP_MASK_RX_LOS_8_15_REG 0x51
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#define CPLD_SFP_MASK_RX_LOS_16_23_REG 0x52
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#define CPLD_SFP_MASK_RX_LOS_24_31_REG 0x53
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#define CPLD_SFP_MASK_RX_LOS_32_39_REG 0x54
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#define CPLD_SFP_MASK_RX_LOS_40_47_REG 0x55
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#define CPLD_SFP_MASK_TX_FAULT_0_7_REG 0x56
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#define CPLD_SFP_MASK_TX_FAULT_8_15_REG 0x57
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#define CPLD_SFP_MASK_TX_FAULT_16_23_REG 0x58
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#define CPLD_SFP_MASK_TX_FAULT_24_31_REG 0x59
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#define CPLD_SFP_MASK_TX_FAULT_32_39_REG 0x5A
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#define CPLD_SFP_MASK_TX_FAULT_40_47_REG 0x5B
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//#define CPLD_SFP_RX_LOS_MASK_BASE_REG 0x50
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//#define CPLD_SFP_TX_FAULT_MASK_BASE_REG 0x56
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#define CPLD_SFP_EVT_RX_LOS_0_7_REG 0x60
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#define CPLD_SFP_EVT_RX_LOS_8_15_REG 0x61
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#define CPLD_SFP_EVT_RX_LOS_16_23_REG 0x62
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#define CPLD_SFP_EVT_RX_LOS_24_31_REG 0x63
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#define CPLD_SFP_EVT_RX_LOS_32_39_REG 0x64
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#define CPLD_SFP_EVT_RX_LOS_40_47_REG 0x65
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#define CPLD_SFP_EVT_TX_FAULT_0_7_REG 0x66
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#define CPLD_SFP_EVT_TX_FAULT_8_15_REG 0x67
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#define CPLD_SFP_EVT_TX_FAULT_16_23_REG 0x68
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#define CPLD_SFP_EVT_TX_FAULT_24_31_REG 0x69
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#define CPLD_SFP_EVT_TX_FAULT_32_39_REG 0x6A
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#define CPLD_SFP_EVT_TX_FAULT_40_47_REG 0x6B
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//#define CPLD_SFP_RX_LOS_EVT_BASE_REG 0x60
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//#define CPLD_SFP_TX_FAULT_EVT_BASE_REG 0x66
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#define CPLD_SFP_TX_DISABLE_0_7_REG 0x70
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#define CPLD_SFP_TX_DISABLE_8_15_REG 0x71
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#define CPLD_SFP_TX_DISABLE_16_23_REG 0x72
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#define CPLD_SFP_TX_DISABLE_24_31_REG 0x73
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#define CPLD_SFP_TX_DISABLE_32_39_REG 0x74
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#define CPLD_SFP_TX_DISABLE_40_47_REG 0x75
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//#define CPLD_SFP_TX_DISABLE_BASE_REG 0x70
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#define CPLD_QSFP_RESET_48_53_REG 0x76
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#define CPLD_QSFP_LPMODE_48_53_REG 0x77
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//debug interrupt status
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#define DBG_CPLD_SFP_INTR_PRESENT_BASE_REG 0xD0
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#define DBG_CPLD_SFP_INTR_PRESENT_0_7_REG 0xD0
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#define DBG_CPLD_SFP_INTR_PRESENT_8_15_REG 0xD1
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#define DBG_CPLD_SFP_INTR_PRESENT_16_23_REG 0xD2
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#define DBG_CPLD_SFP_INTR_PRESENT_24_31_REG 0xD3
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#define DBG_CPLD_SFP_INTR_PRESENT_32_39_REG 0xD4
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#define DBG_CPLD_SFP_INTR_PRESENT_40_47_REG 0xD5
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#define DBG_CPLD_QSFP_INTR_PRESENT_48_53_REG 0xD6
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#define DBG_CPLD_QSFP_INTR_PORT_48_53_REG 0xD7
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//debug interrupt mask
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#define DBG_CPLD_SFP_INTR_RX_LOS_0_7_REG 0xE0
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#define DBG_CPLD_SFP_INTR_RX_LOS_8_15_REG 0xE1
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#define DBG_CPLD_SFP_INTR_RX_LOS_16_23_REG 0xE2
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#define DBG_CPLD_SFP_INTR_RX_LOS_24_31_REG 0xE3
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#define DBG_CPLD_SFP_INTR_RX_LOS_32_39_REG 0xE4
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#define DBG_CPLD_SFP_INTR_RX_LOS_40_47_REG 0xE5
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#define DBG_CPLD_SFP_INTR_TX_FAULT_0_7_REG 0xE6
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#define DBG_CPLD_SFP_INTR_TX_FAULT_8_15_REG 0xE7
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#define DBG_CPLD_SFP_INTR_TX_FAULT_16_23_REG 0xE8
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#define DBG_CPLD_SFP_INTR_TX_FAULT_24_31_REG 0xE9
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#define DBG_CPLD_SFP_INTR_TX_FAULT_32_39_REG 0xEA
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#define DBG_CPLD_SFP_INTR_TX_FAULT_40_47_REG 0xEB
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//#define DBG_CPLD_SFP_RX_LOS_BASE_REG 0xE0
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//#define DBG_CPLD_SFP_TX_FAULT_BASE_REG 0xE6
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//MASK
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#define MASK_ALL (0xFF)
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#define MASK_HB (0b11110000)
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#define MASK_LB (0b00001111)
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#define MASK_CPLD_MAJOR_VER (0b11000000)
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#define MASK_CPLD_MINOR_VER (0b00111111)
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#define CPLD_SYSTEM_LED_SYS_MASK MASK_HB
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#define CPLD_SYSTEM_LED_FAN_MASK MASK_LB
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#define CPLD_SYSTEM_LED_PSU_0_MASK MASK_LB
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#define CPLD_SYSTEM_LED_PSU_1_MASK MASK_HB
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#define CPLD_SYSTEM_LED_SYNC_MASK MASK_LB
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#define CPLD_SYSTEM_LED_ID_MASK MASK_LB
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#define CPLD_SFP_LED_MASK_0 (0b00000011)
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#define CPLD_SFP_LED_MASK_1 (0b00001100)
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#define PERM_R (0b00000001)
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#define PERM_W (0b00000010)
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#define PERM_RW (PERM_R | PERM_W)
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#define IS_PERM_R(perm) (perm & PERM_R ? 1u : 0u)
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#define IS_PERM_W(perm) (perm & PERM_W ? 1u : 0u)
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/* common manipulation */
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#define INVALID(i, min, max) ((i < min) || (i > max) ? 1u : 0u)
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#endif
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