deb9e67838
* [202012] Add SOC property to enable AN/LT on some platforms Why I did it To enable autonegotiation/link training on some Broadcom-based platforms (Arista 7060CX, 7260CX3, 7050cx3, Celestica DX010) How I did it Add appropriate SOC property for enabling the feature to the Broadcom config files of appropriate platforms Also convert line endings to UNIX format for one Celestica file * Add 'phy_an_lt_msft' to BCM config file permitted list
379 lines
6.9 KiB
Plaintext
379 lines
6.9 KiB
Plaintext
# Define default OS / SAL
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os=unix
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# all XPORTs to XE ports
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#pbmp_xport_xe=0x1fffffffe
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pbmp_xport_xe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
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pbmp_oversubscribe=0x1fffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffffe
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# Mode control to select L2 Table DMA mode aka L2MODE_POLL (0) or
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# L2MOD_FIFO mechanism aka L2MODE_FIFO (1) for L2 table change notification.
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l2xmsg_mode=1
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# Memory table size configs
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l2_mem_entries=8192
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l3_mem_entries=8192
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l3_alpm_enable=2
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ipv6_lpm_128b_enable=1
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mmu_lossless=0
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###################################################################################
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# Celestica Customize for SeaStone
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###################################################################################
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#ext mdio frequency to 495/0x80/2(1.933Mhz) or 415/0x80/2(1.62MHz)
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# default is 40
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# Set external MDIO freq to 6.19MHz (495MHz) or 5.19MHz (415MHz)
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#* target_freq is core_clock_freq * DIVIDEND / DIVISOR / 2
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#
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rate_ext_mdio_divisor=0x80
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# use internal rom boot
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phy_ext_rom_boot=0
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#fpem_mem_entries=32768
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oversubscribe_mode=1
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#pbmp_xport_xe=0x3fd000000ff4000003fc000001fe
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dport_map_enable=1
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dport_map_port_68=1
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dport_map_port_72=5
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dport_map_port_76=9
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dport_map_port_80=13
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dport_map_port_34=17
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dport_map_port_38=21
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dport_map_port_42=25
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dport_map_port_46=29
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dport_map_port_50=33
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dport_map_port_54=37
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dport_map_port_58=41
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dport_map_port_62=45
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dport_map_port_84=49
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dport_map_port_88=53
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dport_map_port_92=57
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dport_map_port_96=61
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dport_map_port_102=65
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dport_map_port_106=69
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dport_map_port_110=73
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dport_map_port_114=77
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dport_map_port_1=81
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dport_map_port_5=85
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dport_map_port_9=89
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dport_map_port_13=93
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dport_map_port_17=97
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dport_map_port_21=101
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dport_map_port_25=105
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dport_map_port_29=109
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dport_map_port_118=113
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dport_map_port_122=117
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dport_map_port_126=121
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dport_map_port_130=125
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# port mapping
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portmap_68=65:100:4
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portmap_72=69:100:4
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portmap_76=73:100:4
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portmap_80=77:100:4
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portmap_34=33:100:4
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portmap_38=37:100:4
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portmap_42=41:100:4
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portmap_46=45:100:4
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portmap_50=49:100:4
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portmap_54=53:100:4
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portmap_58=57:100:4
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portmap_62=61:100:4
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portmap_84=81:100:4
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portmap_88=85:100:4
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portmap_92=89:100:4
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portmap_96=93:100:4
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portmap_102=97:100:4
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portmap_106=101:100:4
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portmap_110=105:100:4
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portmap_114=109:100:4
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portmap_1=1:100:4
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portmap_5=5:100:4
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portmap_9=9:100:4
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portmap_13=13:100:4
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portmap_17=17:100:4
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portmap_21=21:100:4
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portmap_25=25:100:4
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portmap_29=29:100:4
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portmap_118=113:100:4
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portmap_122=117:100:4
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portmap_126=121:100:4
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portmap_130=125:100:4
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#portmap_66=129:10
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#portmap_100=131:10
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#WC16
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xgxs_tx_lane_map_68=0x3201
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xgxs_rx_lane_map_68=0x2310
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#WC17
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xgxs_tx_lane_map_72=0x3201
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xgxs_rx_lane_map_72=0x2301
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#WC18
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xgxs_tx_lane_map_76=0x0132
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xgxs_rx_lane_map_76=0x0123
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#WC19
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xgxs_tx_lane_map_80=0x2031
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xgxs_rx_lane_map_80=0x1320
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#WC8
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xgxs_tx_lane_map_34=0x3021
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xgxs_rx_lane_map_34=0x0213
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#WC9
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xgxs_tx_lane_map_38=0x3210
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xgxs_rx_lane_map_38=0x1023
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#WC10
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xgxs_tx_lane_map_42=0x2310
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xgxs_rx_lane_map_42=0x3210
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#WC11
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xgxs_tx_lane_map_46=0x1032
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xgxs_rx_lane_map_46=0x1302
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#WC12
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xgxs_tx_lane_map_50=0x3201
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xgxs_rx_lane_map_50=0x0213
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#WC13
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xgxs_tx_lane_map_54=0x2301
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xgxs_rx_lane_map_54=0x2310
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#WC14
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xgxs_tx_lane_map_58=0x3201
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xgxs_rx_lane_map_58=0x0213
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#WC15
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xgxs_tx_lane_map_62=0x1302
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xgxs_rx_lane_map_62=0x2310
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#WC20
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xgxs_tx_lane_map_84=0x0213
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xgxs_rx_lane_map_84=0x2301
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#WC21
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xgxs_tx_lane_map_88=0x0132
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xgxs_rx_lane_map_88=0x3210
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#WC22
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xgxs_tx_lane_map_92=0x0132
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xgxs_rx_lane_map_92=0x2031
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#WC23
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xgxs_tx_lane_map_96=0x2031
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xgxs_rx_lane_map_96=0x3201
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#WC24
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xgxs_tx_lane_map_102=0x0132
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xgxs_rx_lane_map_102=0x2301
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#WC25
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xgxs_tx_lane_map_106=0x0132
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xgxs_rx_lane_map_106=0x3201
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#WC26
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xgxs_tx_lane_map_110=0x0132
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xgxs_rx_lane_map_110=0x2031
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#WC27
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xgxs_tx_lane_map_114=0x2031
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xgxs_rx_lane_map_114=0x2301
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#WC0
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xgxs_tx_lane_map_1=0x3210
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xgxs_rx_lane_map_1=0x3120
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#WC1
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xgxs_tx_lane_map_5=0x0132
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xgxs_rx_lane_map_5=0x1023
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#WC2
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xgxs_tx_lane_map_9=0x3201
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xgxs_rx_lane_map_9=0x3120
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#WC3
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xgxs_tx_lane_map_13=0x2031
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xgxs_rx_lane_map_13=0x1032
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#WC4
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xgxs_tx_lane_map_17=0x2310
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xgxs_rx_lane_map_17=0x3210
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#WC5
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xgxs_tx_lane_map_21=0x2301
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xgxs_rx_lane_map_21=0x3120
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#WC6
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xgxs_tx_lane_map_25=0x3201
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xgxs_rx_lane_map_25=0x0213
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#WC7
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xgxs_tx_lane_map_29=0x1302
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xgxs_rx_lane_map_29=0x1023
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#WC28
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xgxs_tx_lane_map_118=0x1320
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xgxs_rx_lane_map_118=0x1302
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#WC29
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xgxs_tx_lane_map_122=0x1032
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xgxs_rx_lane_map_122=0x1023
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#WC30
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xgxs_tx_lane_map_126=0x3120
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xgxs_rx_lane_map_126=0x3120
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#WC31
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xgxs_tx_lane_map_130=0x1302
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xgxs_rx_lane_map_130=0x2310
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#PN
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#WC16
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phy_xaui_tx_polarity_flip_68=0x0000
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phy_xaui_rx_polarity_flip_68=0x0000
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#WC17
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phy_xaui_tx_polarity_flip_72=0x000D
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phy_xaui_rx_polarity_flip_72=0x0002
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#WC18
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phy_xaui_tx_polarity_flip_76=0x000F
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phy_xaui_rx_polarity_flip_76=0x0000
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#WC19
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phy_xaui_tx_polarity_flip_80=0x000F
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phy_xaui_rx_polarity_flip_80=0x000F
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#WC8
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phy_xaui_tx_polarity_flip_34=0x000E
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phy_xaui_rx_polarity_flip_34=0x0000
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#WC9
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phy_xaui_tx_polarity_flip_38=0x0008
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phy_xaui_rx_polarity_flip_38=0x0000
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#WC10
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phy_xaui_tx_polarity_flip_42=0x000D
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phy_xaui_rx_polarity_flip_42=0x0000
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#WC11
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phy_xaui_tx_polarity_flip_46=0x0000
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phy_xaui_rx_polarity_flip_46=0x0000
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#WC12
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phy_xaui_tx_polarity_flip_50=0x0002
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phy_xaui_rx_polarity_flip_50=0x0000
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#WC13
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phy_xaui_tx_polarity_flip_54=0x0002
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phy_xaui_rx_polarity_flip_54=0x0000
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#WC14
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phy_xaui_tx_polarity_flip_58=0x0000
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phy_xaui_rx_polarity_flip_58=0x0000
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#WC15
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phy_xaui_tx_polarity_flip_62=0x000A
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phy_xaui_rx_polarity_flip_62=0x000F
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#WC20
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phy_xaui_tx_polarity_flip_84=0x0007
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phy_xaui_rx_polarity_flip_84=0x000E
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#WC21
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phy_xaui_tx_polarity_flip_88=0x000D
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phy_xaui_rx_polarity_flip_88=0x000D
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#WC22
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phy_xaui_tx_polarity_flip_92=0x000F
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phy_xaui_rx_polarity_flip_92=0x0008
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#WC23
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phy_xaui_tx_polarity_flip_96=0x0005
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phy_xaui_rx_polarity_flip_96=0x0000
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#WC24
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phy_xaui_tx_polarity_flip_102=0x0000
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phy_xaui_rx_polarity_flip_102=0x000F
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#WC25
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phy_xaui_tx_polarity_flip_106=0x000F
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phy_xaui_rx_polarity_flip_106=0x0000
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#WC26
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phy_xaui_tx_polarity_flip_110=0x000F
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phy_xaui_rx_polarity_flip_110=0x000F
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#WC27
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phy_xaui_tx_polarity_flip_114=0x000F
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phy_xaui_rx_polarity_flip_114=0x0007
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#WC0
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phy_xaui_tx_polarity_flip_1=0x0003
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phy_xaui_rx_polarity_flip_1=0x000F
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#WC1
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phy_xaui_tx_polarity_flip_5=0x0007
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phy_xaui_rx_polarity_flip_5=0x0000
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#WC2
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phy_xaui_tx_polarity_flip_9=0x0002
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phy_xaui_rx_polarity_flip_9=0x0008
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#WC3
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phy_xaui_tx_polarity_flip_13=0x000F
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phy_xaui_rx_polarity_flip_13=0x0000
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#WC4
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phy_xaui_tx_polarity_flip_17=0x0007
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phy_xaui_rx_polarity_flip_17=0x0000
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#WC5
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phy_xaui_tx_polarity_flip_21=0x0000
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phy_xaui_rx_polarity_flip_21=0x0000
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#WC6
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phy_xaui_tx_polarity_flip_25=0x0002
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phy_xaui_rx_polarity_flip_25=0x0005
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#WC7
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phy_xaui_tx_polarity_flip_29=0x0002
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phy_xaui_rx_polarity_flip_29=0x0000
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#WC28
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phy_xaui_tx_polarity_flip_118=0x000F
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phy_xaui_rx_polarity_flip_118=0x000F
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#WC29
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phy_xaui_tx_polarity_flip_122=0x0004
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phy_xaui_rx_polarity_flip_122=0x0000
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#WC30
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phy_xaui_tx_polarity_flip_126=0x000F
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phy_xaui_rx_polarity_flip_126=0x0000
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#WC31
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phy_xaui_tx_polarity_flip_130=0x0006
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phy_xaui_rx_polarity_flip_130=0x0000
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mmu_init_config="MSFT-TH-Tier0"
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phy_an_lt_msft=1
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