[202012] Add SOC property to enable AN/LT on some platforms (#7547)

* [202012] Add SOC property to enable AN/LT on some platforms

Why I did it
To enable autonegotiation/link training on some Broadcom-based platforms (Arista 7060CX, 7260CX3, 7050cx3, Celestica DX010)

How I did it
Add appropriate SOC property for enabling the feature to the Broadcom config files of appropriate platforms
Also convert line endings to UNIX format for one Celestica file

* Add 'phy_an_lt_msft' to BCM config file permitted list
This commit is contained in:
Joe LeVeque 2021-05-06 22:21:43 -07:00 committed by GitHub
parent f88767b2ce
commit deb9e67838
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
15 changed files with 677 additions and 649 deletions

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@ -514,4 +514,6 @@ serdes_preemphasis_119=0x14410a
serdes_preemphasis_123=0x14410a
serdes_preemphasis_127=0x14410a
serdes_driver_current_130=0xe
serdes_preemphasis_130=0x102804
serdes_preemphasis_130=0x102804
phy_an_lt_msft=1

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@ -558,3 +558,5 @@ serdes_preemphasis_123=0x85804
serdes_preemphasis_125=0x85804
serdes_preemphasis_127=0x85804
serdes_preemphasis_129=0x85804
phy_an_lt_msft=1

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@ -444,3 +444,5 @@ serdes_driver_current_109=0xa
serdes_preemphasis_109=0x284008
mmu_init_config="MSFT-TH-Tier1"
phy_an_lt_msft=1

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@ -545,3 +545,5 @@ serdes_driver_current_115=0xa
serdes_preemphasis_115=0x284008
mmu_init_config="MSFT-TH-Tier0"
phy_an_lt_msft=1

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@ -444,3 +444,5 @@ serdes_driver_current_109=0x4
serdes_preemphasis_109=0x145c00
mmu_init_config="MSFT-TH-Tier1"
phy_an_lt_msft=1

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@ -442,3 +442,5 @@ serdes_driver_current_109=0x4
serdes_preemphasis_109=0x145c00
mmu_init_config="MSFT-TH-Tier0"
phy_an_lt_msft=1

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@ -442,3 +442,5 @@ serdes_driver_current_109=0x4
serdes_preemphasis_109=0x145c00
mmu_init_config="MSFT-TH-Tier1"
phy_an_lt_msft=1

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@ -778,3 +778,5 @@ serdes_driver_current_126=0xa
serdes_preemphasis_126=0x284008
serdes_driver_current_127=0xa
serdes_preemphasis_127=0x284008
phy_an_lt_msft=1

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@ -1035,3 +1035,5 @@ serdes_preemphasis_117=0x133c06
{{ mmu_sock }}
{{ IPinIP_sock }}
phy_an_lt_msft=1

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@ -946,3 +946,5 @@ serdes_preemphasis_131=0x580c
mmu_init_config="MSFT-TH2-Tier0"
{{ IPinIP_sock }}
phy_an_lt_msft=1

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@ -1025,3 +1025,5 @@ serdes_preemphasis_117=0x105004
mmu_init_config="MSFT-TH2-Tier0"
{{ IPinIP_sock }}
phy_an_lt_msft=1

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@ -374,3 +374,5 @@ phy_xaui_tx_polarity_flip_130=0x0006
phy_xaui_rx_polarity_flip_130=0x0000
mmu_init_config="MSFT-TH-Tier0"
phy_an_lt_msft=1

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@ -694,3 +694,5 @@ serdes_preemphasis_lane2_130=0x2b4104
serdes_preemphasis_lane3_130=0x2b4104
mmu_init_config="MSFT-TH-Tier1"
phy_an_lt_msft=1

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@ -91,6 +91,7 @@ phy_an_allow_pll_change_hg
phy_an_c37
phy_an_c73
phy_an_fec
phy_an_lt_msft
phy_automedium
phy_aux_voltage_enable
phy_chain_rx_lane_map_physical