sonic-buildimage/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-Q64
Neetha John 3304fcd3a5 [qos]: Adjust 7260 buffer sizes to accomodate extra lossless queues (#11018)
Why I did it
As part of PCBB changes, we need to enable 2 extra lossless queues. The changes in this PR are done to adjust only the reserved sizes on Th2 for the additional 2 lossless queues
Calculations are done based on 40 downlinks for T1 and 16 uplinks for dual ToR

How to verify it
Verified that the rendering works fine on Th2 dut
Unit tests have been updated to reflect the modified buffer sizes when pcbb is enabled. There are existing testcases that will test the original buffer sizes when pcbb is disabled. With these changes, was able to build sonic-config-engine wheel successfully

Signed-off-by: Neetha John <nejo@microsoft.com>
2022-06-23 02:33:48 +00:00
..
buffers_defaults_t0.j2 [qos]: Adjust 7260 buffer sizes to accomodate extra lossless queues (#11018) 2022-06-23 02:33:48 +00:00
buffers_defaults_t1.j2 [qos]: Adjust 7260 buffer sizes to accomodate extra lossless queues (#11018) 2022-06-23 02:33:48 +00:00
buffers_extra_queues.j2 Add two extra lossless queues for bounced back traffic (#10496) 2022-06-22 23:05:14 +00:00
buffers_pool_sizes_t0.j2 [qos]: Adjust 7260 buffer sizes to accomodate extra lossless queues (#11018) 2022-06-23 02:33:48 +00:00
buffers.json.j2 [MMU] define T1 MMU configuratino for Arista-7260CX3-Q64 (#7718) 2021-05-27 08:20:07 -07:00
config.bcm.j2 [AN/LT][Fix bug]:enable phy_an_lt_msft attribute on some platforms (#11147) 2022-06-16 02:13:22 +00:00
pg_profile_lookup.ini [devices]: PG headroom change for Arista 7260 (#3600) 2019-10-15 06:03:48 -07:00
port_config.ini [HWSKU] Define HWSKU Arista-7260CX3-Q64 and Arista-7260CX3-Q44 (#2562) 2019-02-14 11:27:15 -08:00
qos.json.j2 Update qos config to clear queues for bounced back traffic (#10176) 2022-04-05 22:32:25 +08:00
sai.profile 7260cx3 DualToR config.bcm support based on DualToR setting in device metadata at boot time (#7168) 2021-03-31 14:23:24 -07:00