881796f376
Backport changes from #11018 Signed-off-by: Neetha John <nejo@microsoft.com> Why I did it As part of PCBB changes, we need to enable 2 extra lossless queues. The changes in this PR are done to adjust only the reserved sizes on Th2 for the additional 2 lossless queues Calculations are done based on 40 downlinks for T1 and 16 uplinks for dual ToR How to verify it Verified that the rendering works fine on Th2 dut Unit tests have been updated to reflect the modified buffer sizes when pcbb is enabled. There are existing testcases that will test the original buffer sizes when pcbb is disabled. With these changes, was able to build sonic-config-engine wheel successfully |
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| x86_64-arista_7050_qx32 | ||
| x86_64-arista_7050_qx32s | ||
| x86_64-arista_7050cx3_32s | ||
| x86_64-arista_7050sx3_48yc8 | ||
| x86_64-arista_7060_cx32s | ||
| x86_64-arista_7060cx2_32s | ||
| x86_64-arista_7060dx4_32 | ||
| x86_64-arista_7060px4_32 | ||
| x86_64-arista_7170_32c | ||
| x86_64-arista_7170_32cd | ||
| x86_64-arista_7170_64c | ||
| x86_64-arista_7260cx3_64 | ||
| x86_64-arista_7280cr3_32d4 | ||
| x86_64-arista_7280cr3_32p4 | ||
| x86_64-arista_7800_sup | ||
| x86_64-arista_7800r3_48cq2_lc | ||
| x86_64-arista_7800r3_48cqm2_lc | ||
| x86_64-arista_common | ||
| x86_64-arista_7050sx3_48c8 | ||
| x86_64-arista_7280cr3k_32d4 | ||
| x86_64-arista_7280cr3k_32p4 | ||
| x86_64-arista_7280cr3mk_32d4 | ||
| x86_64-arista_7280cr3mk_32p4 | ||