1acafa4873
Why I did it Add PDDF support on following Ufispace platforms with Broadcom ASIC S9110-32X S8901-54XC S7801-54XS S6301-56ST How I did it Add PDDF configuration files, scripts and python files How to verify it Run pddf commands and show commands. Signed-off-by: nonodark <ef67891@yahoo.com.tw>
150 lines
6.1 KiB
C
150 lines
6.1 KiB
C
/* header file for i2c cpld driver of ufispace_s9110_32x
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*
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* Copyright (C) 2022 UfiSpace Technology Corporation.
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* Jason Tsai <jason.cy.tsai@ufispace.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
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*/
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#ifndef UFISPACE_S9110_32X_CPLD_H
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#define UFISPACE_S9110_32X_CPLD_H
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/* CPLD device index value */
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enum cpld_id {
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cpld1,
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cpld2
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};
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/* CPLD 1 & CPLD 2 registers */
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#define CPLD_NONE_REG 0x00
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#define CPLD_VERSION_REG 0x02
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#define CPLD_ID_REG 0x03
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#define CPLD_BUILD_REG 0x04
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#define CPLD_CHIP_REG 0x05
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#define CPLD_EVT_CTRL_REG 0x3F
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/* CPLD 1 registers */
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#define CPLD_BOARD_ID_0_REG 0x00
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#define CPLD_BOARD_ID_1_REG 0x01
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#define CPLD_SKU_EXT_REG 0x06
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#define CPLD_MAC_INTR_REG 0x10
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#define CPLD_HWM_INTR_REG 0x13
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#define CPLD_CPLD2_INTR_REG 0x14
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#define CPLD_PTP_INTR_REG 0x1B
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#define CPLD_SYSTEM_INTR_REG 0x1C
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#define CPLD_MAC_MASK_REG 0x20
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#define CPLD_HWM_MASK_REG 0x23
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#define CPLD_CPLD2_MASK_REG 0x24
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#define CPLD_PTP_MASK_REG 0x2B
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#define CPLD_SYSTEM_MASK_REG 0x2C
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#define CPLD_MAC_EVT_REG 0x30
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#define CPLD_HWM_EVT_REG 0x33
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#define CPLD_CPLD2_EVT_REG 0x34
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#define CPLD_MAC_RESET_REG 0x40
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#define CPLD_SYSTEM_RESET_REG 0x41
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#define CPLD_BMC_NTM_RESET_REG 0x43
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#define CPLD_USB_RESET_REG 0x44
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#define CPLD_I2C_MUX_RESET_REG 0x46
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#define CPLD_MISC_RESET_REG 0x48
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#define CPLD_BRD_PRESENT_REG 0x50
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#define CPLD_PSU_STATUS_REG 0x51
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#define CPLD_SYSTEM_PWR_REG 0x52
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#define CPLD_MAC_SYNCE_REG 0x53
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#define CPLD_MAC_AVS_REG 0x54
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#define CPLD_SYSTEM_STATUS_REG 0x55
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#define CPLD_WATCHDOG_REG 0x5A
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#define CPLD_BOOT_SELECT_REG 0x5B
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#define CPLD_MUX_CTRL_REG 0x5C
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#define CPLD_MISC_CTRL_1_REG 0x5D
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#define CPLD_MISC_CTRL_2_REG 0x5E
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#define CPLD_MAC_TEMP_REG 0x61
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#define CPLD_SYSTEM_LED_PSU_REG 0x80
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#define CPLD_SYSTEM_LED_SYS_REG 0x81
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#define CPLD_SYSTEM_LED_FAN_REG 0x83
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#define CPLD_SYSTEM_LED_ID_REG 0x84
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#define DBG_CPLD_MAC_INTR_REG 0xE0
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#define DBG_CPLD_HWM_INTR_REG 0xE3
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#define DBG_CPLD_CPLD2_INTR_REG 0xE4
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#define DBG_CPLD_PTP_INTR_REG 0xEB
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/* CPLD 2*/
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#define CPLD_QSFP_ABS_0_7_REG 0x10
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#define CPLD_QSFP_ABS_8_15_REG 0x11
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#define CPLD_QSFP_ABS_16_23_REG 0x12
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#define CPLD_QSFP_ABS_24_31_REG 0x13
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#define CPLD_QSFP_INTR_0_7_REG 0x14
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#define CPLD_QSFP_INTR_8_15_REG 0x15
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#define CPLD_QSFP_INTR_16_23_REG 0x16
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#define CPLD_QSFP_INTR_24_31_REG 0x17
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#define CPLD_SFP_ABS_0_1_REG 0x18
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#define CPLD_SFP_RXLOS_0_1_REG 0x19
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#define CPLD_SFP_TXFLT_0_1_REG 0x1a
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#define CPLD_QSFP_MASK_ABS_0_7_REG 0x20
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#define CPLD_QSFP_MASK_ABS_8_15_REG 0x21
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#define CPLD_QSFP_MASK_ABS_16_23_REG 0x22
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#define CPLD_QSFP_MASK_ABS_24_31_REG 0x23
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#define CPLD_QSFP_MASK_INTR_0_7_REG 0x24
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#define CPLD_QSFP_MASK_INTR_8_15_REG 0x25
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#define CPLD_QSFP_MASK_INTR_16_23_REG 0x26
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#define CPLD_QSFP_MASK_INTR_24_31_REG 0x27
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#define CPLD_SFP_MASK_ABS_0_1_REG 0x28
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#define CPLD_SFP_MASK_RXLOS_0_1_REG 0x29
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#define CPLD_SFP_MASK_TXFLT_0_1_REG 0x2A
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#define CPLD_QSFP_EVT_ABS_0_7_REG 0x30
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#define CPLD_QSFP_EVT_ABS_8_15_REG 0x31
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#define CPLD_QSFP_EVT_ABS_16_23_REG 0x32
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#define CPLD_QSFP_EVT_ABS_24_31_REG 0x33
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#define CPLD_QSFP_EVT_INTR_0_7_REG 0x34
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#define CPLD_QSFP_EVT_INTR_8_15_REG 0x35
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#define CPLD_QSFP_EVT_INTR_16_23_REG 0x36
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#define CPLD_QSFP_EVT_INTR_24_31_REG 0x37
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#define CPLD_SFP_EVT_ABS_0_1_REG 0x38
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#define CPLD_SFP_EVT_RXLOS_0_1_REG 0x39
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#define CPLD_SFP_EVT_TXFLT_0_1_REG 0x3A
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#define CPLD_QSFP_RESET_0_7_REG 0x40
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#define CPLD_QSFP_RESET_8_15_REG 0x41
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#define CPLD_QSFP_RESET_16_23_REG 0x42
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#define CPLD_QSFP_RESET_24_31_REG 0x43
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#define CPLD_QSFP_LPMODE_0_7_REG 0x44
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#define CPLD_QSFP_LPMODE_8_15_REG 0x45
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#define CPLD_QSFP_LPMODE_16_23_REG 0x46
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#define CPLD_QSFP_LPMODE_24_31_REG 0x47
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#define CPLD_SFP_TXDIS_0_1_REG 0x48
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#define CPLD_SFP_TS_0_1_REG 0x49
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#define CPLD_SFP_RS_0_1_REG 0x4A
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#define DBG_CPLD_QSFP_ABS_0_7_REG 0xD0
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#define DBG_CPLD_QSFP_ABS_8_15_REG 0xD1
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#define DBG_CPLD_QSFP_ABS_16_23_REG 0xD2
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#define DBG_CPLD_QSFP_ABS_24_31_REG 0xD3
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#define DBG_CPLD_QSFP_INTR_0_7_REG 0xD4
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#define DBG_CPLD_QSFP_INTR_8_15_REG 0xD5
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#define DBG_CPLD_QSFP_INTR_16_23_REG 0xD6
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#define DBG_CPLD_QSFP_INTR_24_31_REG 0xD7
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#define DBG_CPLD_SFP_ABS_0_1_REG 0xD8
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#define DBG_CPLD_SFP_RXLOS_0_1_REG 0xD9
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#define DBG_CPLD_SFP_TXFLT_0_1_REG 0xDA
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//MASK
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#define MASK_ALL (0xFF)
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#define MASK_NONE (0x00)
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#define MASK_0000_0111 (0x07)
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#define MASK_0011_1111 (0x3F)
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#define MASK_1100_0000 (0xC0)
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/* common manipulation */
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#define INVALID(i, min, max) ((i < min) || (i > max) ? 1u : 0u)
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#endif
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