Commit Graph

24 Commits

Author SHA1 Message Date
bingwang-ms
47d7e5d0d2
[202012] Apply separated DSCP_TO_TC_MAP and TC_TO_QUEUE_MAP on dualtor (#12792)
* Apply separated DSCP_TO_TC_MAP and TC_TO_QUEUE_MAP on dualtor
2022-11-23 21:49:00 +08:00
Ying Xie
778df1e178
[202012][RDMA] create split profiles for Arista-7050CX3-32S (#12478)
* [202012][RDMA] create split profiles for Arista-7050CX3-32S

Manually cherry-picking #12228.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-10-31 22:55:06 -07:00
bingwang-ms
ee7d9d1c45 Map TC6 to Queue 1 for regular traffic (#11904)
Why I did it
This PR is to update TC_TO_QUEUE_MAP|AZURE for SKU Arista-7050CX3-32S-D48C8 and Arista-7260CX3 T0.

The change is only to align the TC_TO_QUEUE_MAP for regular traffic and bounced traffic. It has no impact on business because we have no traffic being mapped to TC2 or TC6.

How I did it
Update TC_TO_QUEUE_MAP|AZURE , and test cases as well.

How to verify it
Verified by running test case test_j2files.py

/sonic/src/sonic-config-engine$ python3 setup.py test -s tests/test_j2files.py
running test
......
----------------------------------------------------------------------
Ran 29 tests in 25.390s

OK
2022-09-17 00:41:48 +00:00
Dev Ojha
8c57f0521f [Arista7050cx3] TD3 SKU changes for pg headroom value after interop testing with cisco 8102 (#11901)
Why I did it
After PFC interop testing between 8102 and 7050cx3, data packet losses were observed on the Rx ports of the 7050cx3 (inflow from 8102) during testing. This was primarily due to the slower response times to react to PFC pause packets for the 8102, when receiving such frames from neighboring devices. To solve for the packet drops, the 7050cx3 pg headroom size has to be increased to 160kB.

How I did it
Modified the xoff threshold value to 160kB in the pg_profile file to allow for the buffer manager to read that value when building the image, and configuring the device

How to verify it
run "mmuconfig -l" once image is built


Signed-off-by: dojha <devojha@microsoft.com>
2022-08-31 11:10:22 -07:00
vmittal-msft
6ada55439d Updated buffer profile settings for TD3 based HWSKUs (Arista-7050CX3-32S-C32, Arista-7050CX3-32S-D48C8) (#11202)
* Updated buffer profile settings for TD3 based HWSKUs (Arista-7050CX3-32S-C32, Arista-7050CX3-32S-D48C8)
2022-07-05 20:57:53 +00:00
bingwang-ms
6ddf5cd7dc
[202012] [cherry-pick] Generate switch level dscp_to_tc_map entry from qos_config template (#11132)
* Generate switch level dscp_to_tc_map

Signed-off-by: bingwang <wang.bing@microsoft.com>
2022-06-17 20:49:56 +08:00
Richard.Yu
f555a4a0a0 [Tunnel PFC] Add property for tunnel PFC (#10962)
* [Tunnel PFC] Add property for tunnel PFC

Replace the config.bcm file with j2 template file
- Add 'sai_remap_prio_on_tnl_egress=1' property when device metadata local
- Host subtype is 'dualtor'
- Change sai.profile foe the new config.bcm.j2
2022-06-05 22:02:19 -07:00
bingwang-ms
e159998657
[202012][cherry-pick] Add two extra lossless queues for bounced back traffic (#10715)
* Add extra lossless queues

Signed-off-by: bingwang <bingwang@microsoft.com>
2022-06-04 19:25:02 +08:00
bingwang-ms
7ec6a60230
[cherry-pick] [202012] Update qos config to clear queues for bounced back traffic (#10608)
* Update qos config to clear queues for bounced back traffic

Signed-off-by: bingwang <wang.bing@microsoft.com>
2022-06-02 16:29:25 +08:00
vmittal-msft
7b7737ef0f Adjustment to ingress pool size to accomodate brcm sai (#10694) 2022-05-03 00:42:27 +00:00
Nikola Dancejic
602c8e99dc
[device config] Adding configuration for default route fallback (#10692)
Set sai_tunnel_underlay_route_mode attribute to fallback to default
route if more specific route is unavailable.
Signed-off-by: Nikola Dancejic <ndancejic@microsoft.com>
2022-04-29 16:20:18 -07:00
vmittal-msft
fcf5dcf5eb Changes to support topology and port speed agnostic switch init for TD3 based platforms (#10587) 2022-04-21 22:00:38 +00:00
Prince Sunny
d6ab409709
[202012] td2/td3 change cpu cos num to 10 (#9311)
Cherry-pick from #9301
2021-11-18 12:48:20 -08:00
gechiang
baa00e6969
[202012] Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9190)
This is to address an issue where it was observed that SAI operations sometime make take a very long to time complete (over 45ms). It was determined that the ALPM distributed thread was causing this issue.
The fix is to disable this debug thread that has no functional purpose.

Preliminary tests looks fine. BGP neighbors were all up with proper routes programmed
interfaces are all up
Manually ran the fib test cases on 7050CX3 (TD3), TD2, TH, TH2, and TH3 based platforms and
thy all passed.
2021-11-08 11:50:44 -08:00
Lawrence Lee
a22c82288d
[device]: Add SAI checksum verify to TD3 config (#8886)
A new config option `sai_verify_incoming_chksum` was added to control the value of IPV4_INCR_CHECKSUM_ORIGINAL_VALUE_VERIFY in the EGR_FLEX_CONFIG control register (this prevents checksums of 0xffff from being propagated to other devices)

Signed-off-by: Lawrence Lee <lawlee@microsoft.com>
2021-10-04 10:45:44 -07:00
gechiang
e784c2607c
[202012] Add BRCM SOC Property to not count ACL drops towards interface RX_DRP fir DualToR platforms (#8000) 2021-07-01 16:45:07 -07:00
Joe LeVeque
deb9e67838
[202012] Add SOC property to enable AN/LT on some platforms (#7547)
* [202012] Add SOC property to enable AN/LT on some platforms

Why I did it
To enable autonegotiation/link training on some Broadcom-based platforms (Arista 7060CX, 7260CX3, 7050cx3, Celestica DX010)

How I did it
Add appropriate SOC property for enabling the feature to the Broadcom config files of appropriate platforms
Also convert line endings to UNIX format for one Celestica file

* Add 'phy_an_lt_msft' to BCM config file permitted list
2021-05-06 22:21:43 -07:00
vmittal-msft
f766a1bccf Updated Qos/MMU settings for Arista-7050CX3-32S-C32 & Arista-7050CX3-32S-D48C8 (#7068)
* TD3 Qos/MMU settings for Arista-7050CX3-32S-C32 & Arista-7050CX3-32S-D48C8
2021-05-05 09:33:19 -07:00
Prince Sunny
75ac46eab0 [Broadcom] Set hierarchical ecmp levels to 2 (#7370)
Set hierarchical ecmp level to 2 instead of 3. Based on CS00011833367, ecmp level must be set to 2.
This is already handled for TH2 platforms. Change is required only for TD3

Co-authored-by: Ubuntu <prsunny@prince-vm.vzw1i4tqyeburcdz5lrgulxi2c.yx.internal.cloudapp.net>
2021-04-21 14:05:31 -07:00
vmittal-msft
61c3816e0c Remove dummy MMU profiles for Arista-7050CX3-32S-C32 and Arista-7050CX3-32S-D48C8 (#6785) 2021-04-19 13:15:55 -07:00
gechiang
fadf10529a [BCM Config] Update TD3 bcm.config files to use ISSU capable premium CANCUN 6.4.1 (#6651) 2021-02-05 16:11:59 -08:00
Tamer Ahmed
6f17c924e6 [sonic-device-data]: Update BRCM Tunnel/ECMP Parameter For 7050cx3 SKUs (#6415)
Update Tunnel and ECMP parameters for brcm 7050cx3 48x50G+8x100G and 32x100G SKUs.

signed-off-by: Tamer Ahmed <tamer.ahmed@microsoft.com>
2021-02-05 16:09:15 -08:00
Ying Xie
1ba583cb46
[TD3] add dummy MMU configuration for Arista-7050CX3-32S-D48C8 (#5950)
Need A mmu configuration to get the device going without generating lots of warnings.

Similar to dummy MMU configuration for Arista-7050CX3-32S-C32, this configuration will need to be updated with correct numbers. This MMU configuration is copied from 7060 comparable hwsku.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2020-11-17 19:01:39 -08:00
Samuel Angebault
4ec83b25bc
[arista]: Add new 48x50G + 8x100G hwsku for Lodoga (#5452) 2020-09-23 22:41:07 -07:00