Commit Graph

888 Commits

Author SHA1 Message Date
Ikki Zhu
cf12aa549a [hlx/sfp] fix hlx platform sfp+ tx disable issue (#11532)
Why I did it:
To fix hlx platform sfp+ module tx disable issue

How I did it:
Fix sfp+ tx disable function according SFF-8472 specification

Co-authored-by: Eric Zhu <erzhu@celestica.com>
2022-08-09 21:05:08 +00:00
bingwang-ms
84aca00847
[202012]Support different DSCP_TO_TC_MAP for T1 in dualtor deployment (#11580)
Why I did it
This PR is to backport #11569 into 202012 branch.
This PR is to apply different DSCP_TO_TC_MAP to downlink and uplink ports on T1 in dualtor deployment.
For T1 downlink ports (To T0)
The DSCP_TO_TC_MAP is not changed. DSCP2 and DSCP6 are mapped to TC2 and TC6 respectively.
For T1 uplink ports (To T1)
A new DSCP_TO_TC_MAP|AZURE_UPLINK is defined and applied. DSCP2 and DSCP6 are mapped to TC1 to avoid mixing up lossy and lossless traffic from T2.
The extra lossy PG2 and PG6 added in PR #11157 is reverted as well because no traffic from T2 is mapped to PG2 or PG6 now.

How I did it
Define a new map DSCP_TO_TC_MAP|AZURE_UPLINK for 7260 T1.

How to verify it
Verified by test case in test_j2files.py.
2022-08-01 08:59:45 -07:00
Stephen Sun
44ecff1154
Support queue 7 in dual ToR scenario (#11570)
Signed-off-by: Stephen Sun <stephens@nvidia.com>
2022-08-01 09:27:49 +08:00
Kebo Liu
c40435c94c
[202012] [Mellanox] Add new sensor conf to support SN4410 A1 system (#8379) (#11530)
- Why I did it
New SN410 A1 system has a different sensor layout with A0 system, needs a new sensor conf file to support it.

- How I did it
Since the SN4410 A1 system use exactly the same sensor layout as the SN4700 A1 system, so add a symbol link linking to the SN4700 A1 sensor conf file to reuse.

- How to verify it
Run sensor test against the SN4410 A1 system;
Run platform related regression test against the SN4410 A1 system
2022-07-29 17:41:44 +02:00
Taylor Cai
c4927e0e68 [device/celestica]:Fix failed test case of Seastone snmp (#11430)
* Update psu.py
* Update thermal.py
2022-07-27 23:28:11 +00:00
Neetha John
15cc046eda
[202012] Update MMU and ECN settings for Arista-7260CX3-D96C16 (#11427)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
Missed this sku in the previous PR #11398

How I did it
Update the dynamic threshold to 0 and ECN settings as 2mb/10mb/5%

How to verify it
Updated unit tests to use the modified values for 7260 ecn settings.
2022-07-15 09:33:39 -07:00
Kebo Liu
aa4379ddbe
[202012] [Mellanox] Add sensor conf file for new version of MSN3700/3700C/4600C platforms (#11358)
- Why I did it
MSN3700/3700C/4600C have been re-spined, the new HW version of platforms has different sensors, so need to apply the correct sensor.conf for them.

- How I did it
Add new sensor.conf files for the new re-spined platforms.
Enhance the logic of "get_sensors_conf_path" for the related platforms in order to load the correct sensor.conf for each version of platforms.

- How to verify it
run sensors test on different versions of platforms
Signed-off-by: Kebo Liu <kebol@nvidia.com>
2022-07-14 08:59:10 +03:00
Neetha John
4de610af15
[202012] Update 7260 MMU and ECN settings (#11398)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
Improve throughput and latency for 7260 deployments

How I did it
Update the dynamic threshold to 0 and ECN settings as 2mb/10mb/5%

How to verify it
Updated unit tests to use the modified values for 7260 ecn settings.
2022-07-12 08:46:44 -07:00
Ying Xie
1d55dca6d3 [Buffer] Separate buffer profile for Arista-7060CX-32S-Q24C8
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-07-07 14:09:01 -07:00
Ying Xie
17a9259c55 [7060] fix default port map
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-07-07 14:09:01 -07:00
Kevin Wang
41518aa825 [Buffer] Separate buffer profile for Arista-7260CX3-Q64
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-07 14:09:01 -07:00
Kevin Wang
f53b2620db [Buffer] Separate buffer profile for Arista-7260CX3-D108C8
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-07 14:09:01 -07:00
Kevin Wang
b625085b46 [Buffer] Separate buffer profile for Arista-7260CX3-C64
50G data is not accurate, needs further update.

Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-07 14:09:01 -07:00
Kevin Wang
5b42ba021b [Buffer] Separate buffer profile for Arista-7060CX-32S-C32
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-07 14:09:01 -07:00
Kevin Wang
83780549c7 [Buffer] Separate buffer profile for Arista-7060CX-32S-D48C8
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-07 14:09:01 -07:00
Kevin Wang
e8f04cd2e6 [Buffer] Separate buffer profile for Arista-7060CX-32S-Q32
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-07 14:09:01 -07:00
Kevin Wang
2c81f02b13 [Buffer] Separate buffer profile for Celestica-DX010-D48C8
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-07 14:09:01 -07:00
Kevin Wang
4dbdc8e0a0 [Buffer] Separate buffer profile for Force10-S6100
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-07 14:09:01 -07:00
Ying Xie
2ed29da38d [buffer] create infrastructure to enable buffer/QoS profiles
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-07-07 14:09:01 -07:00
vmittal-msft
6ada55439d Updated buffer profile settings for TD3 based HWSKUs (Arista-7050CX3-32S-C32, Arista-7050CX3-32S-D48C8) (#11202)
* Updated buffer profile settings for TD3 based HWSKUs (Arista-7050CX3-32S-C32, Arista-7050CX3-32S-D48C8)
2022-07-05 20:57:53 +00:00
Stephen Sun
fe6be5da92
[202012] Configure different map between uplink and downlink on t1 switch in dual ToR scenario (#11299)
- Why I did it
Configure different DSCP_TO_TC_MAP between uplink and downlink on T1 switch in dual ToR scenario
On T1 uplink, both DSCP 2/6 will be mapped to TC 1 for the purpose of avoiding such traffic occupying lossless buffers.
On T1 downlink, they will be mapped to TC 2/6 respectively. (unchanged)

- How I did it
For vendors who want to configure different DSCP_TO_TC_MAP between uplinks and downlinks on T1, they should
Define generate_dscp_to_tc_map macro in SKU's qos.json.j2 file
Define map AZURE for downlink and AZURE_UPLINK for uplink
Define jinja2 variable different_dscp_to_tc_map as True

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2022-07-03 15:58:06 +03:00
Stephen Sun
307d0e2aca
[Mellanox][202012] Support Mellanox-SN4600C-C64 as T1 switch in dual-ToR scenario (#11032)
Why I did it
Support Mellanox-SN4600C-C64 as T1 switch in dual-ToR scenario

1. Support additional queue and PG in buffer templates, including both traditional and dynamic model
2. Support mapping DSCP 2/6 to lossless traffic in the QoS template.
3. Add macros to generate additional lossless PG in the dynamic model
4. Adjust the order in which the generic/dedicated (with additional lossless queues) macros are checked and called to generate buffer tables in common template buffers_config.j2
  - Buffer tables are rendered via using macros.
  - Both generic and dedicated macros are defined on our platform. Currently, the generic one is called as long as it is defined, which causes the generic one always being called on our platform. To avoid it, the dedicated macrio is checked and called first and then the generic ones.
5. Support MAP_PFC_PRIORITY_TO_PRIORITY_GROUP on ports with additional lossless queues.

On Mellanox-SN4600C-C64, buffer configuration for t1 is calculated as:
40 * 100G downlink ports with 4 lossless PGs/queues, 1 lossy PG, and 3 lossy queues
16 * 100G uplink ports with 2 lossless PGs/queues, 1 lossy PG, and 5 lossy queues

Signed-off-by: Stephen Sun stephens@nvidia.com

How to verify it
Run regression test.
2022-06-21 10:04:49 -07:00
bingwang-ms
6ddf5cd7dc
[202012] [cherry-pick] Generate switch level dscp_to_tc_map entry from qos_config template (#11132)
* Generate switch level dscp_to_tc_map

Signed-off-by: bingwang <wang.bing@microsoft.com>
2022-06-17 20:49:56 +08:00
Jon Goldberg
159613153f [Nokia ixs7215] change var/log size to 4GB (#11122)
This makes use of #11121 to add support for configuration of VAR_LOG_SIZE on Nokia IXS7215
2022-06-14 09:02:14 -07:00
Guohan Lu
b0c48f9b31 [devices]: fix j2 syntax error for the config.bcm in Arista-7260CX3-D108C8
Signed-off-by: Guohan Lu <lguohan@gmail.com>
2022-06-10 11:23:28 -07:00
Neetha John
881796f376
[202012] Adjust 7260 buffer sizes to accomodate extra lossless queues (#11050)
Backport changes from #11018

Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
As part of PCBB changes, we need to enable 2 extra lossless queues. The changes in this PR are done to adjust only the reserved sizes on Th2 for the additional 2 lossless queues
Calculations are done based on 40 downlinks for T1 and 16 uplinks for dual ToR

How to verify it
Verified that the rendering works fine on Th2 dut
Unit tests have been updated to reflect the modified buffer sizes when pcbb is enabled. There are existing testcases that will test the original buffer sizes when pcbb is disabled. With these changes, was able to build sonic-config-engine wheel successfully
2022-06-06 18:13:16 -07:00
Guohan Lu
693bc5faae Revert "[qos]: Adjust 7260 buffer sizes to accomodate extra lossless queues (#11018)"
This reverts commit 21f14dc6ea.

unit test needs to be cherry-picked.
2022-06-06 06:30:24 -07:00
Neetha John
21f14dc6ea [qos]: Adjust 7260 buffer sizes to accomodate extra lossless queues (#11018)
Why I did it
As part of PCBB changes, we need to enable 2 extra lossless queues. The changes in this PR are done to adjust only the reserved sizes on Th2 for the additional 2 lossless queues
Calculations are done based on 40 downlinks for T1 and 16 uplinks for dual ToR

How to verify it
Verified that the rendering works fine on Th2 dut
Unit tests have been updated to reflect the modified buffer sizes when pcbb is enabled. There are existing testcases that will test the original buffer sizes when pcbb is disabled. With these changes, was able to build sonic-config-engine wheel successfully

Signed-off-by: Neetha John <nejo@microsoft.com>
2022-06-05 22:23:13 -07:00
Richard.Yu
f555a4a0a0 [Tunnel PFC] Add property for tunnel PFC (#10962)
* [Tunnel PFC] Add property for tunnel PFC

Replace the config.bcm file with j2 template file
- Add 'sai_remap_prio_on_tnl_egress=1' property when device metadata local
- Host subtype is 'dualtor'
- Change sai.profile foe the new config.bcm.j2
2022-06-05 22:02:19 -07:00
bingwang-ms
e159998657
[202012][cherry-pick] Add two extra lossless queues for bounced back traffic (#10715)
* Add extra lossless queues

Signed-off-by: bingwang <bingwang@microsoft.com>
2022-06-04 19:25:02 +08:00
bingwang-ms
7ec6a60230
[cherry-pick] [202012] Update qos config to clear queues for bounced back traffic (#10608)
* Update qos config to clear queues for bounced back traffic

Signed-off-by: bingwang <wang.bing@microsoft.com>
2022-06-02 16:29:25 +08:00
Taylor Cai
f5ecf1ee1c [device/celestica]:Fix failed test case of Haliburton snmp (#10844) 2022-05-25 22:56:57 +00:00
Vivek R
cd0a0608a9 Removed platform specific reboot files for mellanox simx platforms (#10806)
- Why I did it
Platform_reboot files for simx doesn't do aything different apart from calling /sbin/reboot. which is anyway done in the /usr/local/bin/reboot script i.e. the parent script which calls the platform specific reboot scripts if present.

Moreover, /sbin/reboot invoked in the platform specific reboot script is a non-blocking call and thus it returns back to the original script (although /sbin/reboot does it job in the background) and we see messages like this.

Signed-off-by: Vivek Reddy Karri <vkarri@nvidia.com>
2022-05-16 23:28:02 +00:00
vmittal-msft
7b7737ef0f Adjustment to ingress pool size to accomodate brcm sai (#10694) 2022-05-03 00:42:27 +00:00
Nikola Dancejic
602c8e99dc
[device config] Adding configuration for default route fallback (#10692)
Set sai_tunnel_underlay_route_mode attribute to fallback to default
route if more specific route is unavailable.
Signed-off-by: Nikola Dancejic <ndancejic@microsoft.com>
2022-04-29 16:20:18 -07:00
Taylor Cai
1aeb658964 Fix issue test_crm and test_fib (#10585)
Why I did it
Fix issue (https://github.com/Azure/sonic-buildimage/issues/9171) and (https://github.com/Azure/sonic-buildimage/issues/9236)

How I did it
Add flag in config file for get correct count of IPv6 entry.
Add init config file to set IPv4 ECMP hash on L4.

How to verify it
Compile the sonic_platform wheel for e1031, then upload to device and install the wheel, verify using testbed.
2022-04-26 17:40:47 +00:00
vmittal-msft
fcf5dcf5eb Changes to support topology and port speed agnostic switch init for TD3 based platforms (#10587) 2022-04-21 22:00:38 +00:00
Eric Zhu
8a246b88b1 Fix issue of partially parsing syseeprom value (#10020) (#10276)
Why I did it
The current code assumes that the value part does not have whitespace. So everything after the whitespace will be ignored. The syseeprom values returned from platform API do not match the output of "show platform syseeprom" on dx010 and e1031 device.

How I did it
This change improved the regular expression for parsing syseeprom values to accommodate whitespaces in the value.
PR 10021 provides the solution, but committed to the wrong place for dx010 and e1031.

How to verify it
Compile the sonic_platform wheel for dx010, then upload to device and install the wheel, verify the platform eeprom API.

Signed-off-by: Eric Zhu <erzhu@celestica.com>
2022-03-25 21:53:45 +00:00
zzhiyuan
49af3bbf0b
[202012] [Arista] Add Arista-7260CX3-D96C16 HWSKU (#10197)
This was an ask by Microsoft to provide:
7260 config.bcm file for hardware sku Arista-7260CX3-D92C16 (Named Arista-7260CX3-D96C16).

There are 16 100G uplinks:
Ethernet13-20/1
Ethernet45-52/1

All other ports are breakout to 2 50G ports.

The original ask was for 201811. This is the requested PR for 202012.

How I did it
Copied existing Arista-7260CX3-D108C8 HWSKU and altered the bcm config, port_config.ini, and buffers config files.

Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
2022-03-23 14:32:54 -07:00
abdosi
c3ede8eb5d Fix Headroom value for 7260C64 SKU (#10075)
Updated the Headroom value for (100G,5m) in 7260C64 SKU.
2022-03-01 22:49:11 +00:00
Aravind Mani
331db09f88 Dell S6100: Addition of 10G ports (#9988) 2022-02-23 22:46:20 +00:00
Aravind Mani
6752e2131d [Dell S6100] Addition of 10G ports (#9906) 2022-02-23 22:46:14 +00:00
Kebo Liu
85dc6892e1 fix MSN4410 chassis name in platform_components.json (#9939)
- Why I did it
The chassis name in MSN4410 platform_components.json is not correct

- How I did it
Fix the chassis name

- How to verify it
Run relevant platform API test

Signed-off-by: Kebo Liu <kebol@nvidia.com>
2022-02-15 23:56:50 +00:00
abdosi
4932b4202e Added 40G {300/40/5m} pg lookup profile for 7260 100G SKU (#9249)
What I did:
Added 40G {300/40/5m} profile for 7260 100G SKU
2022-02-09 19:47:44 +00:00
Junchao-Mellanox
0f983c5796 [Mellanox] Fix issue: SN4600C has 4 CPU core temperature sensors (#9930)
- Why I did it
platform.json of 4600C only has 2 CPU core thermal sensors, but there are 4 actually

- How I did it
Added thermal sensors for CPU core 2 and core 3.

- How to verify it
Build.
2022-02-09 19:27:49 +00:00
vdahiya12
73b27b7c9e
fix build error (#9902)
Signed-off-by: vaibhav-dahiya <vdahiya@microsoft.com>
2022-02-03 08:52:29 +05:30
Christian Svensson
d3df3c9e93 [Celestica/Seastone2] Load interface LEDs (#9769)
Tested on a Celestica Seastone2 DX030 switch

Testing scenarios:
- Various QSFP ports in both normal and breakout config.
- 100G and 40G link speed show different colors.
- SFP1 port works.

Signed-off-by: Christian Svensson <blue@cmd.nu>
2022-01-25 22:17:40 +00:00
gechiang
068ff9ddbd
[202012][BRCM TH3] Add SOC properties to prevent FDB events during warmboot (#9761) 2022-01-14 14:44:43 -08:00
Kebo Liu
75bd97e176 [Mellanox] Add sensors conf for MSN4600C A1 platform (#9706)
- Why I did it
Add sensor conf for MSN4600C A1 platform

- How I did it
Add a new sensor conf file and relevant scripts to support two different versions of the platform

- How to verify it
Run "sensors" cmd to check the output on the A1 platform to see whether it's as expected.
Signed-off-by: Kebo Liu <kebol@nvidia.com>
2022-01-13 07:01:26 +00:00
Stephen Sun
b36ee67bc7 Fix typo and missing files in SN3800 and SN4600C's buffer templates (#9537)
Why I did it
Fix typo and missing files in SN3800 and SN4600C's buffer templates

How I did it
ingress_lossless_xoff_size => ingress_lossless_pool_xoff add missing files for SN4600C-D100C12S2

How to verify it
Deploy the fix and verify whether the device can be up.

Signed-off-by: Stephen Sun <stephens@nvidia.com>
2021-12-23 03:28:43 +00:00