Calls to sonic-cfggen is CPU expensive. This PR reduces calls to
sonic-cfggen to once calle during snmp startup
singed-off-by: Tamer Ahmed <tamer.ahmed@microsoft.com>
`quilt` may leave behind a `.pc/` directory, which will show up in `git status`. Delete it if it is present as part of cleaning up after `quilt` operations.
Changes:
-- Correct Pattern for VLAN.
-- Add Special Test support.
-- Add first special test to load VLAN 1-4094.
-- Add lanes in ports.
-- Make Sure None test gets no output from libyang while config load.
[yangModelTesting.py]: INCORRECT VLAN_NAME FIELD IN VLAN TABLE test.
Signed-off-by: Praveen Chaudhary pchaudhary@linkedin.com
As part of migrating all Python-based package installers to wheel format rather than Debian packages. Also to allow for easily building a Python 3 version of the package in the near future. ledd and psud were converted in earlier PRs. This PR converts the remainder:
- pcied
- syseepromd
- thermalctld
- xcvrd
Modify port_config.ini files multi-asic vs platform. Changes done:
- Add new columns: index, asic_port_name, role(Int/Ext)
- Modify alias of interface names. Alias should match the interface names present in minigraph file.
Signed-off-by: SuvarnaMeenakshi <sumeenak@microsoft.com>
[db_migrator] Support migrating database regarding buffer configuration for all Mellanox switches (#993)
[show/vlan]: fix show vlan config (#1050)
[PFCWD] Fix issue with "pfcwd show stats" command during SONiC init (#1018)
[config] Eliminate port breakout-related globals (#1045)
[teamshow]: refactor teamshow to use state db information (#1049)
[watermarkstat] Import print_function from __future__ (#1048)
[show]: split show interfaces commands into separate file (#1044)
Python 3 compliance (#1043)
Update all references to new 'sonic-installer' file name (#1033)
[config/show]: split vlan into separate file (#1038)
[pytest/coverage]: add coverage for all scripts (#1041)
enable watchdog before running platform specific reboot plugin (#1037)
[tests]:add coverage for config/main/utilities_common module (#1039)
[cli/feature]: split feature command into a separate file (#1034)
Signed-off-by: Stephen Sun <stephens@nvidia.com>
Co-authored-by: Stephen Sun <stephens@mellanox.com>
As part of migrating all Python-based package installers to wheel format rather than Debian packages. Also to allow for easily building a Python 3 version of the package in the near future.
Signed-off-by: Arvindsrinivasan Lakshmi Narasimhan arlakshm@microsoft.com
The following common APIs are added for multi ASIC
- an API to check if a given port is a internal or external port
- an API to check if a given port-channel is internal or external
- an API to check if a bgp-session is internal or external
- an API to connect to the config and other dbs in the a given namespace
- added common APIs to the sonic_py_common library.
- update the sample port-config.ini with role column and add corresponding test to verify the ports configuration is - generated properly.
As part of migrating all Python-based package installers to wheel format rather than Debian packages. Also to allow for easily building a Python 3 version of the package in the near future.
- Also remove some references to sonic-daemon-base which I previously missed and add missing sonic-py-common dependency for sonic-pcied.
Original converting from register is wrong, it makes the fan speed much higher than it is. Change the way fan speed is calculated from CPLD.
Signed-off-by: roy_lee <roy_lee@accton.com>
Calculate pool size in t1 as 24 * downlink port + 8 * uplink port
- Take both port and peer MTU into account when calculating headroom
- Worst case factor is decreased to 50%
- Mellanox-SN2700-C28D8 t0, assume 48 * 50G/5m + 8 * 100G/40m ports
- Mellanox-SN2700 (C32)
- t0: 16 * 100G/5m + 16 * 100G/40m
- t1: 16 * 100G/40m + 16 * 100G/300m
Signed-off-by: Stephen Sun <stephens@mellanox.com>
Co-authored-by: Stephen Sun <stephens@mellanox.com>
HW set qsfp port to reset at default. so need SW to set to normal when boot.
1. Modify cpld driver to invert reset offset value
2. Set to normal when boot.
Calls to cfggen take considerable time. With batch mode, we will have the ability
to reduce number of calls from services.
Example of the batch mode command:
sonic-cfggen -t template-1.j2 -t template-2.j2,config-db -t template-3.j2,config-db -t template-4.j2,file1 -t template-5.j2,file2 --write-to-db.
template-1.j2 will be rendered to stdout since it is missing the dest part. stdout is default
config-db is a special keyword that will inject the rendered template into internal data structure. The internal data structure gets written to redis-db with --write-to-db switch. In the case the user would like to write to a file named config-db, it could be given as /config-db or ./config-db
signed-off-by: Tamer Ahmed <tamer.ahmed@microsoft.com>
python3-swsscommon is newly added build target besides originally python2 version of swsscommon library. Add this target to buildimage rules so we could make target/debs/buster/python3-swsscommon_1.0.0_amd64.deb
NUM_ASIC environment variable was added so that it could be used by other utilities.
This is not being used by any other utility or docker, hence removing the addition of NUM_ASIC environment variable.
Also, the environment variable was added by adding the variable value to /etc/environ file.
Upon each reboot, this file gets updated with the NUM_ASIC value but the existing value was not removed.
This causes multiple lines getting appended in /etc/environ file upon each reboot.
Signed-off-by: SuvarnaMeenakshi <sumeenak@microsoft.com>
Swap order of orchagent and portsyncd in start.sh and fix priorities
Many docker virtual switch tests are failing at the moment because orchagent never finishes initializing. After doing some searching I figured out that Ethernet24 is never published to State DB, which is reminiscent of #4821
Signed-off-by: Danny Allen <daall@microsoft.com>
* Bring up FPGA ports and test it
* Bring up those ports in neighbors dict
* Revert delete of a line
* Add test
* change code comment
* Change test name
* Revert submodule update
* src/sonic-utilities 9700e45...621aad0 (9):
> [Python] Migrate applications/scripts to import sonic-py-common package (#1008)
> [config qos] QoS and Buffer config genration for multi ASIC platforms (#978)
> [cli]: pass db connector as click context (#1029)
> [PDDF] Make utilities compatible to platform API 2.0, in accordance with pddf_2.0 (#940)
> [tests] Add unit tests for 'show platform ...' commands (#1021)
> Add secure fast/warm-reboot support for Aboot (#994)
> [sonic-installer] Create Envvars File for Incoming Image (#1011)
> [config load]: do not stop/reset/reload service if it is disabled (#1028)
> [tests]: move feature_test.py into tests folder (#1027)
* src/sonic-ztp c959371...dd025bc (2):
> Update all references to new 'sonic-installer' file name (#18)
> Filter out non-printable characters read from syseeprom (#17)
Removes installation of kube-proxy (117 MB) and flannel (53 MB) images from Kubernetes-enabled devices. These images are tested to be unnecessary for our use case, as we do not rely on ClusterIPs for Kubernetes Services or a CNI for pod networking.
* src/sonic-platform-common be1cc24...f3f3573 (3):
> Remove sonic-config-engine dependency from setup.py (#109)
> Migrate from sonic-daemon-base package to sonic-py-common package (#103)
> [Cables] Add support for 'Extended Specification Compliance' for QSFP cables (#108)
> [sfputilbase.py] Add application_advertisement NA field to transceiver_info_dict for platform api 1.0 (#104)
* src/sonic-platform-daemons 49d145c...8e0704e (1):
> Proper fix for thermalctld using sonic-py-common (#80)
> Fix thermalctld tests which were broken by the transition to sonic-py-common (#79)
> Migrate from sonic-daemon-base package to sonic-py-common package (#74)
summary of E530 platfrom:
- CPU: CTC5236, arm64
- LAN switch chip set: CENTEC CTC7132 (TsingMa). TsingMa is a purpose built device to address the challenge in the recent network evolution such as Cloud computing. CTC7132 provides 440Gbps I/O bandwidth and 400Gcore bandwidth, the CTC7132 family combines a feature-rich switch core and an embedded ARM A53 CPU Core running at 800MHz/1.2GHz. CTC7132 supports a variety of port configurations, such as QSGMII and USXGMII-M, providing full-rate port capability from 100M to 100G.
- device E530-48T4X: 48 * 10/100/1000 Base-T Ports, 4 * 10GE SFP+ Ports.
- device E530-24X2C: 24 * 10 GE SFP+ Ports, 2 * 100GE QSFP28 Ports.
add new files in three directories:
device/centec/arm64-centec_e530_24x2c-r0
device/centec/arm64-centec_e530_48t4x_p-r0
platform/centec-arm64
Co-authored-by: taocy <taocy2@centecnetworks.com>
Co-authored-by: Gu Xianghong <gxh2001757@163.com>
Co-authored-by: shil <shil@centecnetworks.com>
