Commit Graph

13 Commits

Author SHA1 Message Date
Sambath Kumar Balasubramanian
da348ecb79 sonic-buildimage Remove unused SAT port from arista configs. (#14167)
Why I did it
To fix aristanetworks/sonic#85

How I did it
Remove unnecessary SAT ports

How to verify it
Speed change from 400-100g without any error.
2023-03-14 04:32:42 +08:00
mssonicbld
6083175d06
[device/arista] Reduce SDK stat polling freq in DNX devices (#13429) (#13604) 2023-02-03 07:53:34 +08:00
kenneth-arista
63bdc43b7f [device/arista] Disabled polled_irq_mode for DNX SKUs (#13349)
Disabled polled_irq_mode for all Arista DNX devices as this mode
leads to excessive use of the CPU via an unneeded interrupt
polling thread.
2023-01-21 04:32:08 +08:00
Tejaswini Chadaga
3c485e02b2
[202205] Update BRCM SAI version to 7.1.31.4 (#13346)
Why I did it
To bring in the following fixes:

Revert temporary fix added to disable SA equal DA drops
CS00012273013 - [7.1][J2, J2c+] Disable SA Equals DA trap on DNX
CS00012274222 - How to block the voq for given destination port for a flow from a remote mod-id
CS00012275381 - SAI_INGRESS_PRIORITY_GROUP_STAT_PACKETS is incremented for port's PG's even if there are no traffic sent to that PG
CS00012274433 - Local Fault and Remote Fault are not polled by linkscan thread
How I did it
Merged above fixes to SAI code

How to verify it
Validated by running the basic sanity tests on XGS and DNX chassis platforms including

fib/test_fib.py
decap/test_decap.py
drop_counters/test_drop_counters.py
arp/test_arpall.py
2023-01-12 23:49:24 -08:00
mssonicbld
109275ac2a
Fix missing system_ref_core_clock_khz (#12663) (#13074)
Add missing system_ref_core_clock_khz in Arista-7800R3A-36D2-C36 and Arista-7800R3A-36D2-C72

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-12-17 00:26:19 -08:00
mssonicbld
332480f4eb
DNX(J2/J2c/J2c+): Reserve Non-ECMP Fec Resource for Non-ECMP Route Nexthops/NBR Entries (#13076) (#13089) 2022-12-17 15:12:34 +08:00
mssonicbld
fd6523b423
Fix port index for multi-asic (#13042) (#13086)
Port indexes of front panel ports are not contiguous in multi-asic because we didn't distiguish between
front panel and internal ports, e.g., recycle ports. Fix this by assigning index to front panel port first
and then internal ports.

Co-authored-by: Song Yuan <64041228+ysmanman@users.noreply.github.com>
2022-12-16 14:56:12 -08:00
vmittal-msft
89ac469d62 Updated config files to disable DLR_INIT capability (#12401) 2022-10-25 20:42:28 +00:00
Sambath Kumar Balasubramanian
1d627f73c8
[Chassis][Voq] Update bcm config file system_ref_core_clock_khz param for j2cplus linecards. (#11760)
Update the bcm config file system_ref_core_clock_khz param to
handlesystems with J2cplus linecards.
We need system_ref_core_clock_khz to be set to 1600000 for supporting j2
and j2cplus linecards on the same chassis.
2022-08-19 16:15:12 -07:00
kenneth-arista
2280f3854c [Arista] Enable larger number of LAGs on 7800 LCs (#11070)
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.

Why I did it
The SOC property changes are necessary to match #10519 which increases the number of system LAG IDs to 1024.

Description for the changelog
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.
2022-08-08 20:40:54 +00:00
vmittal-msft
8035e3d9a7 Updated Chassis MMU settings for 40G/100G/400G line cards (#11108)
* Updated Chassis MMU settings for 40G/100G/400G line cards
2022-07-05 16:10:50 +00:00
arista-nwolfe
b3672c1f57
Setting the soc property for num_sa_per_sc on macsec encrypt/decrypt (cherry-pick of PR 11166) (#11279) 2022-07-05 09:06:24 -07:00
Maxime Lorrillere
392899682f
[Arista] Add support for Wolverine linecards (#8887)
Add support for WolverineQCpu, WolverineQCpuMs, WolverineQCpuBk, WolverineQCpuBkMs

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-05-20 14:11:06 -07:00