Commit Graph

11 Commits

Author SHA1 Message Date
gechiang
068ff9ddbd
[202012][BRCM TH3] Add SOC properties to prevent FDB events during warmboot (#9761) 2022-01-14 14:44:43 -08:00
gechiang
baa00e6969
[202012] Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9190)
This is to address an issue where it was observed that SAI operations sometime make take a very long to time complete (over 45ms). It was determined that the ALPM distributed thread was causing this issue.
The fix is to disable this debug thread that has no functional purpose.

Preliminary tests looks fine. BGP neighbors were all up with proper routes programmed
interfaces are all up
Manually ran the fib test cases on 7050CX3 (TD3), TD2, TH, TH2, and TH3 based platforms and
thy all passed.
2021-11-08 11:50:44 -08:00
gechiang
8915e488b7
[202012] BRCM Disable ACL Drop counted towards interface RX_DRP counters (#8383)
* [202012] BRCM Disable ACL Drop counted towards interface RX_DRP counters
2021-08-11 09:10:17 -07:00
Samuel Angebault
468aac92b7
[Arista] Update platform configurations for 7060DX4 and 7060PX4 (#6084)
Current support for the 7060PX4-32 and 7060DX4 was broken.
With this change, ports are now linking fine.

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2020-12-04 10:11:06 -08:00
zzhiyuan
3da996bbf8
[arista]: Add disable_pcie_firmware_check soc property (#5543)
This is to fix pcie firmware check assert in Broadcom SDK once the SAI changes merges. This will be in the future but adding the soc property in the broadcom config now.

Co-authored-by: Zhi Yuan Carl Zhao <zyzhao@arista.com>
2020-10-06 18:35:15 -07:00
abdosi
a6a10f05b7
In SAI 3.5 by default we are supporting 256 Group with 64 Memeber each. (#5400)
However in SAI 3.7 default behaviout got changes to 128 Group and 128
    Memeber each.

    This change is to make sure we are using same ECMP Group/Memeber Per
    Group for 3.7 also so that behaviour is consistent.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2020-09-22 11:21:12 -07:00
Samuel Angebault
de4fa1874a
[arista]: remove the soc property disabling sram scan (#4623) 2020-05-20 12:44:48 -07:00
zzhiyuan
1840bef1a1 [devices]: Add serdes tuning for Arista 7060PX4 32x400G (#3382) 2019-08-28 08:44:13 -07:00
zzhiyuan
16e85712b7 [devices]: Add tuning for Arista 7060PX/DX4 32x400G (#3145)
* Add serdes polarity for 32x400G Arista 7060PX/DX4

* Add serdes polarity for 64x100G on Arista 7060PX/DX4
2019-07-12 11:25:19 -07:00
Samuel Angebault
d84aa49d38 [device/Arista] Add HwSku profiles for the 7060PX-32 (#2973)
* Add port configuration for HWSKU Arista-7060PX4-O32

* Add 64x100G configuration for 7060PX4-32
2019-06-06 15:38:11 -07:00
zzhiyuan
6037707abc [devices]: Add device data for Arista 7060PX/DX4-32 (#2534)
* Add boot0 definition for Arista 7060PX4-32 and 7060DX4-32

* Add port configuration for Arista 7060PX4-32

* Add plugins for Arista 7060PX4-32

* Add platform_reboot for Arista 7060PX4-32

* Add Arista 7060DX4-32 as symlink of 7060PX4-32

* Add sensors configuration and fancontrol for Arista 7060PX4-32

* Update arista-driver submodules for barefoot/broadcom

* Add platform_reboot script for Alhambra

* Rook fancontrol CPLD rename
2019-02-08 22:02:01 -08:00