Commit Graph

303 Commits

Author SHA1 Message Date
mssonicbld
ca123ca2a5
[Arista] Update hwsku.json for Arista-7050QX-32S-S4Q31 (#15251) (#15671)
* [Arista] Update hwsku.json for Arista-7050QX-32S-S4Q31

* Change to 3x10G(3)+1x1G(1) on Arista-7050QX-32S-S4Q31

Co-authored-by: byu343 <byu@arista.com>
2023-06-30 13:24:54 -07:00
mssonicbld
a1990d4c48
[Arista][x86_64-arista_7050_qx32] Add Components to platform.json (#15252) (#15585) 2023-06-23 03:41:58 +08:00
vmittal-msft
41cd22d04e
Updated default ECN settings for T2 chassis (#15541)
* Updated default ECN settings for T2 chassis (#14388)

Why I did it
Update ECN settings for T2 chassis

How I did it
Updated qos config file to load these settings during switch bootup

How to verify it
Verified on line card on T2 chassis

* Fix for test failures

* Test case failures

* test case fix
2023-06-22 08:17:45 -07:00
Samuel Angebault
3396cca1a3 [Arista] fix platform.json for a few devices (#15308)
Why I did it
sonic-mgmt is failing tests due to invalid test data in platform.json
Fwutil is upset the chassis name in the platform_component.json of the 7060CX-32S

How I did it
Fixed the aforementioned issues
2023-06-16 09:55:06 +08:00
Arvindsrinivasan Lakshmi Narasimhan
2e15db02f2 set the default value for the port fec to RS on J2 based LC (#15346)
Why I did it
Work item tracking
Microsoft ADO (24182162):
How I did it
update the config.bcm to set the default fec RS 100G Linecard

How to verify it
Tests on chassis
2023-06-10 14:32:40 +08:00
vmittal-msft
723c508a30
Update PG headroom settings ports based on port speed/cable length (#15287)
Why I did it
Update cable length for uplink/downlink ports for chassis and and update PG/pool headroom size accordingly.

Work item tracking
17880812

How I did it
Updated cable length as well as buffer config in HWSKU files.
2023-06-02 15:48:11 -07:00
Neetha John
9f66b28068
[202205][brcm] Fix alignment of soc properties (#15240)
Why I did it
To improve readability of config.bcm, fixed the alignment of soc properties

How to verify it
Build sonic_config_engine-1.0-py3-none-any.whl successfully

Signed-off-by: Neetha John <nejo@microsoft.com>
2023-05-30 16:15:32 -07:00
Neetha John
8661e9de2c
[202205] Update SOC properties for DLR_INIT based pfcwd recovery (#15217)
Why I did it
Update soc properties for certain roles that need to use pfcwd dlr init based recovery mechanism

How to verify it
Updated the templates on a 7050cx3 dual tor and 7260 T1 which satisfies these conditions and validated pfcwd recovery which uses DLR_INIT based mechanism. Also validated that this mechanism is not used on 7050cx3 single tor with the updated templates

Signed-off-by: Neetha John <nejo@microsoft.com>
2023-05-26 14:29:34 -07:00
arista-nwolfe
9f8a250f61
Add soc property sai_pfc_dlr_init_capability=0 to missing DNX SKUs (#15155) 2023-05-26 09:08:40 -07:00
mssonicbld
4cdcda43b8
[devices/arista] Update asic_port_name in Arista LCs (#14234) (#14732)
Updated asic_port_names for all Arista LC SKUs to follow latest naming
conventions to remove redundant ASICx suffix. For
Arista-7800R3-48CQ2-C48, added the asic_port_name mapping.

Co-authored-by: kenneth-arista <93353051+kenneth-arista@users.noreply.github.com>
2023-04-19 23:08:03 -07:00
mssonicbld
01311046ca
[devices/arista]: Added recycle ports required for egress mirroring (#13967) (#14731) 2023-04-20 05:56:32 +08:00
Samuel Angebault
9ac78190ee [Arista] Add missing platform_components.json (#14067)
Provide platform-components.json for Clearwater2 and Wolverine

These files are needed for fwutil platform sonic-mgmt tests to pass.

Fix PikeZ platform_components.json

Co-authored-by: Patrick MacArthur <pmacarthur@arista.com>
Co-authored-by: Andy Wong <andywong@arista.com>
2023-03-16 04:32:32 +08:00
Sambath Kumar Balasubramanian
da348ecb79 sonic-buildimage Remove unused SAT port from arista configs. (#14167)
Why I did it
To fix aristanetworks/sonic#85

How I did it
Remove unnecessary SAT ports

How to verify it
Speed change from 400-100g without any error.
2023-03-14 04:32:42 +08:00
kenneth-arista
812c1aeecf
sonic-buildimage Make changes to arista config.bcm files to support max cores (#13831) (#14033)
To support 64 cores on arista skus. Fixes aristanetworks/sonic#77
Remapped recycle ports to lowers core port ids and set appl_param_nof_ports_per_modid to 64.

Co-authored-by: Sambath Kumar Balasubramanian <63021927+skbarista@users.noreply.github.com>
2023-03-02 13:08:00 -08:00
mssonicbld
ab6b3cde4e
Add QOS profiles for Arista SKUs (#13829) (#14040) 2023-03-02 14:51:41 +08:00
Samuel Angebault
3c3a4ac517 [Arista] update sensors.conf to ignore sensors (#12529)
Why I did it
The sensors and sensord processes were reporting data on unused sensors.
This lead to ALARM messages or erroneous values that could be misinterpreted.

How I did it
Ignore the affected sensors in the sensors.conf

How to verify it
Check that there are no longer ALARM messages from sensord in the syslog or in the output of sensors
2023-02-22 04:33:53 +08:00
mssonicbld
cdbdf95e70
fix platform.json on Wolverine for thermal sensors (#13524) (#13748)
Why I did it
The current platform.json contains entries for thermals and SFPs that do not exist on Wolverine.

How I did it
I removed the incorrect entries.

How to verify it
Verify using applicable sonic-mgmt platform API tests.

Co-authored-by: Patrick MacArthur <patrick@patrickmacarthur.net>
2023-02-10 14:39:00 -08:00
mssonicbld
c5998be1e2
[Arista] Add other chassis names to platform_components.json for 720DT-48S (#12378) (#13744)
Why I did it
The 720DT-48S platform has variants with different chassis names, and these need to all be included in platform_components.json to ensure that sonic-mgmt platform_tests/fwutil/test_fwutil.py::test_fwutil_show passes

How I did it
Updated platform_components.json with the variant names for 720DT-48S.

How to verify it
Ran aforementioned testcase and verified that it passes on the different variants.

Co-authored-by: andywongarista <78833093+andywongarista@users.noreply.github.com>
2023-02-10 09:15:57 -08:00
mssonicbld
6083175d06
[device/arista] Reduce SDK stat polling freq in DNX devices (#13429) (#13604) 2023-02-03 07:53:34 +08:00
mssonicbld
900b809e12
[Arista] [Platform] Update platform.json for psu led (#13523) (#13583) 2023-02-02 05:18:55 +08:00
kenneth-arista
63bdc43b7f [device/arista] Disabled polled_irq_mode for DNX SKUs (#13349)
Disabled polled_irq_mode for all Arista DNX devices as this mode
leads to excessive use of the CPU via an unneeded interrupt
polling thread.
2023-01-21 04:32:08 +08:00
Ying Xie
07baa17a32 [Arista] add support for hardware sku Arista-7260CX3-D92C16 (#13438)
Signed-off-by: Ying Xie <ying.xie@microsoft.com>

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2023-01-20 06:33:02 +08:00
Tejaswini Chadaga
3c485e02b2
[202205] Update BRCM SAI version to 7.1.31.4 (#13346)
Why I did it
To bring in the following fixes:

Revert temporary fix added to disable SA equal DA drops
CS00012273013 - [7.1][J2, J2c+] Disable SA Equals DA trap on DNX
CS00012274222 - How to block the voq for given destination port for a flow from a remote mod-id
CS00012275381 - SAI_INGRESS_PRIORITY_GROUP_STAT_PACKETS is incremented for port's PG's even if there are no traffic sent to that PG
CS00012274433 - Local Fault and Remote Fault are not polled by linkscan thread
How I did it
Merged above fixes to SAI code

How to verify it
Validated by running the basic sanity tests on XGS and DNX chassis platforms including

fib/test_fib.py
decap/test_decap.py
drop_counters/test_drop_counters.py
arp/test_arpall.py
2023-01-12 23:49:24 -08:00
andywongarista
4a6c954e90 [Arista] Update ip packet checksum when set to 0xffff on 720DT-48S (#13088)
Why I did it
This is to fix test_forward_ip_packet_with_0xffff_chksum_tolerant test failure on 720DT-48S. IP packets with checksum set to 0xffff will be forwarded with the same checksum on this platform, instead of updating to the correct value.

How I did it
Add bcm config sai_verify_incoming_chksum=0 so that checksum is updated instead of being left unchanged when checksum is 0xffff. Note that packets with invalid checksum are still dropped with this config.
2023-01-05 12:37:20 +08:00
byu343
3226d06e3d [Arista]: Add hwSku Arista-7260CX3-D108C10 (#13242)
* [Arista]: Add hwSku Arista-7260CX3-D108C10

* Add buffer-related config for Arista-7260CX3-D108C10
2023-01-05 10:51:31 +08:00
mssonicbld
109275ac2a
Fix missing system_ref_core_clock_khz (#12663) (#13074)
Add missing system_ref_core_clock_khz in Arista-7800R3A-36D2-C36 and Arista-7800R3A-36D2-C72

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-12-17 00:26:19 -08:00
mssonicbld
332480f4eb
DNX(J2/J2c/J2c+): Reserve Non-ECMP Fec Resource for Non-ECMP Route Nexthops/NBR Entries (#13076) (#13089) 2022-12-17 15:12:34 +08:00
mssonicbld
e1791fef42
Revert "[Arista] Disable pcie checking on x86_64-arista_7050cx3_32s (#12900)" (#13085)
This reverts commit dd87a791b4.

Co-authored-by: vaibhav-dahiya <vdahiya@microsoft.com>
2022-12-16 16:00:40 -08:00
mssonicbld
fd6523b423
Fix port index for multi-asic (#13042) (#13086)
Port indexes of front panel ports are not contiguous in multi-asic because we didn't distiguish between
front panel and internal ports, e.g., recycle ports. Fix this by assigning index to front panel port first
and then internal ports.

Co-authored-by: Song Yuan <64041228+ysmanman@users.noreply.github.com>
2022-12-16 14:56:12 -08:00
kenneth-arista
d410ebe645 Add aggregate port_config.ini for Wolverine SKU (#12951)
Add missing aggregate port_config.ini needed by sonic-mgmt

Concatenate the ASIC specific port_config.ini from device/arista/x86_64-arista_7800r3a_36d2_lc/Arista-7800R3A-36D2-C36/[01] to create the aggregate file.
2022-12-15 16:38:11 +08:00
mssonicbld
943ea1b005
[arista] Add platform.json for arista chassis LC5 (#12949) (#13027) 2022-12-13 07:39:07 +08:00
byu343
6a718a3685 [Arista] Disable pcie checking on x86_64-arista_7050cx3_32s (#12900)
This change is to disable the pcie firmware check done by Broadcom SAI. The change is needed for the Arista platform x86_64-arista_7050cx3_32s; otherwise, the check will fail, blocking the initialization.

There was a pcie firmware check added in brcm SDK and certain Arista hardwares do not compliant with the check, so we added the disable_pcie_firmware_check originally for x86_64-arista_7060dx4_32. For x86_64-arista_7050cx3_32s, it was able to pass the check but some firmware change done in August made it fail.
2022-12-09 06:32:36 +08:00
Jing Kan
f0f143ea62 [Arista 720DT] Create SKU alias Arista-720DT-G48S4 (#12905) 2022-12-08 04:32:58 +08:00
andywongarista
465cd9db8b [Arista] Enable ipv6 128b lpm on 720DT-48S (#12832)
Why I did it
Added to allow test_crm_route to pass; the test tries to add a /126 ipv6 route and this change is required in order for the count of available routes to be updated correctly.
2022-12-01 01:36:29 +00:00
Samuel Angebault
c9e467be7d [Arista] Update platform.json for 7060CX-32S (#12783)
Why I did it
Some sonic-mgmt platform_tests/api were failing on the 7060CX-32S

How I did it
Added the missing metadata in platform.json and platform_components.json
This is purely test data and does not impact our API implementation.

How to verify it
Run platform_tests / api and expect 100% pass rate.
2022-11-28 18:51:52 +00:00
Samuel Angebault
d32a3af99c [Arista] Update platform.json for 7260CX3-64 (#12757)
Why I did it
Some sonic-mgmt platform_tests/api were failing on the 7260CX3-64

How I did it
Added the missing metadata in platform.json and platform_components.json
This is purely test data and does not impact our API implementation.

How to verify it
Run platform_tests/api and expect 100% passrate.
2022-11-28 18:51:13 +00:00
bingwang-ms
4f7a0b4705 Apply separated DSCP_TO_TC_MAP and TC_TO_QUEUE_MAP to uplink ports on dualtor (#12730)
Why I did it
The PR is to apply separated DSCP_TO_TC_MAP and TC_TO_QUEUE_MAP to uplink ports on dualtor.
The traffic with DSCP 2 and DSCP 6 from T1 is treated as lossless traffic.

DSCP    TC    Queue
2      2     2
6      6     6
Traffic with DSCP 2 or DSCP 6 from downlink is still treated as lossy traffic as before.

How I did it
Define DSCP_TO_TC_MAP|AZURE_UPLINK and TC_TO_QUEUE_MAP|AZURE_UPLINK.

How to verify it
Verified by UT
Verified by coping the new template to a testbed, and rendering a config_db.json
2022-11-28 18:51:04 +00:00
wenyiz2021
547d3df694 [Arista] [platform] Add thermal info in platform.json (#12714)
add 1 more thermal entry
2022-11-28 18:50:55 +00:00
wenyiz2021
e663d7ea72 [arista] [chassis] Add psu/thermal info in platform.json for sup (#12667)
update psu info in platform.json on sup
2022-11-28 18:50:12 +00:00
Neetha John
92ae2bda5d [Profile separation] MMU infrastructure update for TD2 (#12626)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
There is a need to have separate profiles on compute and storage and this infra update will help achieve that

How I did it
Moved buffer pool/profile and qos definitions on TD2 to a common folder and all TD2 hwsku's will reference that folder
2022-11-28 18:49:47 +00:00
Bohan Yang
18bdd154a6 [Arista]Add media_settings.json for x86_64-arista_7800r3a_36d2_lc (#12444)
Why I did it
TX FIR tuning should be done based on the type of inserted transceiver

How I did it
Add media_settings.json which contains the tuning data for 100G optic and 400G optic.

How to verify it
Tested against x86_64-arista_7800r3a_36d2_lc
2022-11-28 18:49:17 +00:00
andywongarista
c086987fc4
Mark thermals as not controllable (#12393) 2022-11-21 14:38:22 -08:00
wenyiz2021
aaea93ce2d [Chassis] [Arista] correct platform.json for sup and LC6 names (#12627)
add platform.json separately for LC6 that has different name, bc of supporting macsec
Signed-off-by: Wenyi Zhang <wenyizhang@microsoft.com>
2022-11-10 18:15:58 +00:00
arlakshm
ce45f23a57 [chassis][Arista] add supervisor to the platform_env.conf (#12615)
Why I did it
Fixes #12614

How I did it
In the container_checker the database_chassis is added to expected container if device is supervisor
To detect the device is superviso, add supervisor=1 to the platform_env.conf of 7808 sup platform

How to verify it
run container_checker monit check
Signed-off-by: Arvindsrinivasan Lakshmi Narasimhan <arlakshm@microsoft.com>
2022-11-10 18:15:42 +00:00
judyjoseph
ab713dcfb6 Use the macsec_enabled flag in platform to enable macsec feature state (#11998)
* Use the macsec_enabled flag in platform to enable macesc feature state
* Add macsec supported metadata in DEVICE_RUNTIME_METADATA
2022-11-10 18:08:42 +00:00
vmittal-msft
89ac469d62 Updated config files to disable DLR_INIT capability (#12401) 2022-10-25 20:42:28 +00:00
Ying Xie
6578b9d790 [RDMA] create split profiles for Arista-7050CX3-32S (#12228)
Moving buffer configuration files to sub folders to enable multiple buffer profiles. Otherwise, non-functional change.

Signed-off-by: Ying Xie ying.xie@microsoft.com
2022-10-25 20:37:57 +00:00
Bohan Yang
08da4efe34 Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards. (#11872)
Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards.
2022-10-25 20:36:37 +00:00
Sambath Kumar Balasubramanian
a4d6676f83 Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards. (#11813)
Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards.
2022-10-25 20:35:45 +00:00
andywongarista
2b36f81063
[202205][Arista] Fix content of platform.json for DCS-7050CX3-32S (#12265)
* Fix platform.json for 7050cx3

* Add platform_components.json
2022-10-06 08:05:46 -07:00