Commit Graph

11 Commits

Author SHA1 Message Date
vmittal-msft
9a15221e46
Update CPU transmitted packets to queue 7 for chassis (#16254)
* Update CPU transmitted packets to TC = 7 for SONIC chassis

* Added new SOC property to permitted list
2023-08-29 18:33:16 -07:00
Arvindsrinivasan Lakshmi Narasimhan
0f194c5a03
set the default value for the port fec to RS on J2 based LC (#15346)
Why I did it
Work item tracking
Microsoft ADO (24182162):
How I did it
update the config.bcm to set the default fec RS 100G Linecard

How to verify it
Tests on chassis
2023-06-08 11:08:48 -07:00
arista-nwolfe
990993e3f4
[devices/arista]: Added recycle ports required for egress mirroring (#13967)
Why I did it
Support Egress Mirroring on supported Arista platforms

How I did it
Add necessary soc properties for egress mirroring recycle ports to be created

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>
2023-04-06 10:58:01 -07:00
Sambath Kumar Balasubramanian
d1bca210a6
sonic-buildimage Make changes to arista config.bcm files to support max cores (#13831)
To support 64 cores on arista skus. Fixes aristanetworks/sonic#77
Remapped recycle ports to lowers core port ids and set appl_param_nof_ports_per_modid to 64.
2023-02-23 17:54:43 -08:00
kenneth-arista
8c2d8ea4af
[device/arista] Reduce SDK stat polling freq in DNX devices (#13429)
Eariler the SDK stat polling was erroneously set to once every msec
which is far more frequent than required by SWSS. The new setting, which
is consistent with other vendor SKUs, is once a second. The net result
is reduced CPU MHz by syncd.
2023-01-30 14:13:01 -08:00
kenneth-arista
06d55b8027
[device/arista] Disabled polled_irq_mode for DNX SKUs (#13349)
Disabled polled_irq_mode for all Arista DNX devices as this mode
leads to excessive use of the CPU via an unneeded interrupt
polling thread.
2023-01-12 23:48:37 -08:00
vmittal-msft
cca17ce104
Updated config files to disable DLR_INIT capability (#12401) 2022-10-18 10:13:07 -07:00
kenneth-arista
a4b9838231
[Arista] Enable larger number of LAGs on 7800 LCs (#11070)
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.

Why I did it
The SOC property changes are necessary to match #10519 which increases the number of system LAG IDs to 1024.

Description for the changelog
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.
2022-07-06 14:42:45 -07:00
Sambath Kumar Balasubramanian
699c4e5bbf
[chassis][voq]Update bcm config file system_ref_core_clock_khz param for j2cplus linecards (#11212)
Update the bcm config file system_ref_core_clock_khz param to handlesystems with J2cplus linecards.

We need system_ref_core_clock_khz to be set to 1600000 for supporting j2 and j2cplus linecards on the same chassis.
2022-06-23 08:03:08 -07:00
byu343
da43edcf3e
[arista] Update serdes tuning values for 7800r3_48cqm2 (#9967)
This update the serdes tuning values for Arista 7800r3_48cqm2. The values are for the optical transceivers.
2022-04-12 15:53:35 -07:00
Samuel Angebault
17f0217f30
[Arista] Chassis device configurations (#7529)
Add configurations for the following chassis elements

Fabrics 7804R3-FM, 7808R3-FM and 7808R3A-FM
Linecard 7800R3-48CQ2
Supervisor 7800-SUP*
2021-06-30 18:16:20 -07:00