Commit Graph

1069 Commits

Author SHA1 Message Date
Neetha John
765741ac73
Update 7260 MMU and ECN settings (#11449)
Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
Improve throughput and latency for 7260 deployments

How I did it
Update the dynamic threshold to 0 and ECN settings as 2mb/10mb/5%

How to verify it
Updated unit tests to use the modified values for 7260 ecn settings.
2022-07-18 17:08:20 -07:00
Marty Y. Lok
c8cbd82abb
[Nokia][IXR7250E] Add Nokia platform Nokia-IXR7250E-36x100GE 100G line card device dat (#11382)
Signed-off-by: mlok <marty.lok@nokia.com>
2022-07-14 08:14:34 -07:00
Ying Xie
503a0f7088 [Buffer] Separate buffer profile for Arista-7060CX-32S-Q24C8
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-07-12 11:48:01 -07:00
Ying Xie
aee63310f6 [7060] fix default port map
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-07-12 11:48:01 -07:00
zzhiyuan
55e72a3397 [Arista] [201811] Add Arista-7260CX3-D96C16 HWSKU (#10034)
Why I did it
This was an ask by Microsoft to provide:
7260 config.bcm file for hardware sku Arista-7260CX3-D92C16 (Named Arista-7260CX3-D96C16).

There are 16 100G uplinks:
Ethernet13-20/1
Ethernet45-52/1

All other ports are breakout to 2 50G ports.

How I did it
Copied existing Arista-7260CX3-D108C8 HWSKU and altered the bcm.config and port_config.ini files.

How to verify it
The new 100G ports do come up with a 201811 image using this HWSKU.

Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
2022-07-12 11:48:01 -07:00
Kevin Wang
b8b7a0f4fc [Buffer] Separate buffer profile for Arista-7260CX3-Q64
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-12 11:48:01 -07:00
Kevin Wang
96dc42d0b9 [Buffer] Separate buffer profile for Arista-7260CX3-D108C8
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-12 11:48:01 -07:00
Kevin Wang
dba7b21b30 [Buffer] Separate buffer profile for Arista-7260CX3-C64
50G data is not accurate, needs further update.

Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-12 11:48:01 -07:00
Kevin Wang
fc88c1350e [Buffer] Separate buffer profile for Arista-7060CX-32S-C32
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-12 11:48:01 -07:00
Kevin Wang
686ad1883d [Buffer] Separate buffer profile for Arista-7060CX-32S-D48C8
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-12 11:48:01 -07:00
Kevin Wang
1219766600 [Buffer] Separate buffer profile for Arista-7060CX-32S-Q32
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-12 11:48:01 -07:00
Kevin Wang
e5d77d779d [Buffer] Separate buffer profile for Celestica-DX010-D48C8
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-12 11:48:01 -07:00
Kevin Wang
cd21ee33dc [Buffer] Separate buffer profile for Force10-S6100
Signed-off-by: Kevin Wang <shengkaiwang@microsoft.com>
2022-07-12 11:48:01 -07:00
Ying Xie
61b52a2af7 [buffer] create infrastructure to enable buffer/QoS profiles
Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2022-07-12 11:48:01 -07:00
Lawrence Lee
1b7fcb4659
[device]: Add SAI checksum verify to TD3 config (#8857)
* [device]: Add SAI checksum verify to TD3 config
* A new config option was added to control the value of IPV4_INCR_CHECKSUM_ORIGINAL_VALUE_VERIFY in the EGR_FLEX_CONFIG control register (this prevents checksums of 0xffff from being propagated to other devices)
2022-07-07 22:31:21 -07:00
kenneth-arista
a4b9838231
[Arista] Enable larger number of LAGs on 7800 LCs (#11070)
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.

Why I did it
The SOC property changes are necessary to match #10519 which increases the number of system LAG IDs to 1024.

Description for the changelog
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.
2022-07-06 14:42:45 -07:00
Samuel Angebault
7b98cf35c3
[Arista] Update configurations for 7800R3A-36D2 (#10987)
Why I did it
This linecard runs in multi-asic mode and therefore needs the use_pcie_id_chassis file to work properly.
The default_sku file was also missing which would break the boot when no minigraph is provided.

Description for the changelog
Add missing default_sku and use_pci_id_chassis configs for 7800R3A-36D2
2022-07-05 18:57:52 -07:00
Polly Hsu
fe679ac965
[as7816-64x] Update to support DPB (Dynamic Port Breakout) (#10562)
Signed-off-by: polly_hsu polly_hsu@edge-core.com

Why I did it
Update to support as7816-64x DPB (Dynamic Port Breakout)

How I did it
Download the SONiC master image with commit, 64dc08a dated 2022-04-05 from SONiC Image Azure Pipelines
Update the file change of this PR accordingly

How to verify it
Set the default t1 topology configuration
Configure to breakout Ethernet0 from "1x100G[40G]" to "4x25G"
$ sudo config interface breakout Ethernet0 "4x25G" -f
Check the SONiC DBP interface status is expected
$ show interfaces status
2022-06-30 12:29:11 -07:00
Andrew Sapronov
7f10b6bc35
[Netberg][Barefoot] Added support for Aurora 610 (#10579)
Why I did it
Support Intel Tofino based platforms Netberg Aurora 610
ASIC: Intel Tofino BFN-T10-032D-020
Pors: 48x 25G + 8x 100G

How I did it
Added specification to device/netberg directory
Added platform/barefoot/sonic-platform-modules-netberg contains kernel modules, scripts and sonic_platform packages.
Modified the platform/barefoot/one-image.mk and platform/barefoot/rule.mk to include Aurora 610 related ID and files.

How to verify it
Build SONiC

Install the image on the device and verify the related components are installed and shown correctly.
2022-06-30 10:40:47 -07:00
WistronNetwork
df28eceb35
[Wistron] Add 6512-32r platform support (#10956)
Why I did it
Add 6512-32r support for Wistron platform
Update sw-to3200k for newer branch
How I did it
Add code in device and platform folder for 6512-32r
Update sw-to3200k code both in device and platform folder
How to verify it
Install on Wistron device and run command to verify

Signed-off-by: RogerChang Roger_Chang@wistron.com
2022-06-30 09:13:56 -07:00
andywongarista
6e0559d5fa
[Arista] Add initial support for 720DT-48S (#10656)
Added initial set of config files to allow for booting and partial traffic testing in SONiC on the 720DT-48S.

How to verify it
- Switch boots
- show interfaces status shows links up on interfaces Ethernet24-51
- Traffic flows with no errors on interfaces Ethernet24-51
2022-06-29 09:56:24 -07:00
bingwang-ms
ac86f71287
Add extra lossy PG profile for ports between T1 and T2 (#11157)
Signed-off-by: bingwang <wang.bing@microsoft.com>

Why I did it
This PR brings two changes

Add lossy PG profile for PG2 and PG6 on T1 for ports between T1 and T2.
After PR Update qos config to clear queues for bounced back traffic #10176 , the DSCP_TO_TC_MAP and TC_TO_PG_MAP is updated when remapping is enable

DSCP_TO_TC_MAP
Before	After	Why do this change
"2" : "1"	"2" : "2"	Only change for leaf router to map DSCP 2 to TC 2 as TC 2 will be used for lossless TC
"6" : "1"	"6" : "6"	Only change for leaf router to map DSCP 6 to TC 6 as TC 6 will be used for lossless TC

TC_TO_PRIORITY_GROUP_MAP
Before	After	Why do this change
"2" : "0"	"2" : "2"	Only change for leaf router to map TC 2 to PG 2 as PG 2 will be used for lossless PG
"6" : "0"	"6" : "6"	Only change for leaf router to map TC 6 to PG 6 as PG 6 will be used for lossless PG

So, we have two new lossy PGs (2 and 6) for the T2 facing ports on T1, and two new lossless PGs (2 and 6) for the T0 facing port on T1.
However, there is no lossy PG profile for the T2 facing ports on T1. The lossless PGs for ports between T1 and T0 have been handled by buffermgrd .Therefore, We need to add lossy PG profiles for T2 facing ports on T1.

We don't have this issue on T0 because PG 2 and PG 6 are lossless PGs, and there is no lossy traffic mapped to PG 2 and PG 6

Map port level TC7 to PG0
Before the PCBB change, DSCP48 -> TC 6 -> PG 0.
After the PCBB change, DSCP48 -> TC 7 -> PG 7
Actually, we can map TC7 to PG0 to save a lossy PG.

How I did it
Update the qos and buffer template.

How to verify it
Verified by UT.
2022-06-28 12:50:33 -07:00
arista-nwolfe
19dcfd3328
Setting the soc property for num_sa_per_sc on macsec encrypt and decrypt (#11166)
* Setting the soc property for num_sa_per_sc on macsec encrypt and decrypt
* Changed decrypt from 2 to 4 to match broadcom's recommendations
2022-06-27 12:53:57 -07:00
vmittal-msft
981454767d
Updated Chassis MMU settings for 40G/100G/400G line cards (#11108)
* Updated Chassis MMU settings for 40G/100G/400G line cards
2022-06-23 10:03:59 -07:00
Sambath Kumar Balasubramanian
699c4e5bbf
[chassis][voq]Update bcm config file system_ref_core_clock_khz param for j2cplus linecards (#11212)
Update the bcm config file system_ref_core_clock_khz param to handlesystems with J2cplus linecards.

We need system_ref_core_clock_khz to be set to 1600000 for supporting j2 and j2cplus linecards on the same chassis.
2022-06-23 08:03:08 -07:00
vmittal-msft
b8707f7a6d
Updated buffer profile settings for TD3 based HWSKUs (Arista-7050CX3-32S-C32, Arista-7050CX3-32S-D48C8) (#11202)
* Updated buffer profile settings for TD3 based HWSKUs (Arista-7050CX3-32S-C32, Arista-7050CX3-32S-D48C8)
2022-06-22 21:55:17 -07:00
Kebo Liu
7ac590b5c5
[Mellanox] Enhance Platform API to support SN2201 - RJ45 ports and new components mgmt. (#10377)
* Support new platform SN2201 and RJ45 port

Signed-off-by: Kebo Liu <kebol@nvidia.com>

* remove unused import and redundant function

Signed-off-by: Kebo Liu <kebol@nvidia.com>

* fix error introduced by rebase

Signed-off-by: Kebo Liu <kebol@nvidia.com>

* Revert the special handling of RJ45 ports (#56)

* Revert the special handling of RJ45 ports

sfp.py
sfp_event.py
chassis.py

Signed-off-by: Stephen Sun <stephens@nvidia.com>

* Remove deadcode

Signed-off-by: Stephen Sun <stephens@nvidia.com>

* Support CPLD update for SN2201

A new class is introduced, deriving from ComponentCPLD and overloading _install_firmware
Change _install_firmware from private (starting with __) to protected, making it overloadable

Signed-off-by: Stephen Sun <stephens@nvidia.com>

* Initialize component BIOS/CPLD

Signed-off-by: Stephen Sun <stephens@nvidia.com>

* Remove swb_amb which doesn't on DVT board any more

Signed-off-by: Stephen Sun <stephens@nvidia.com>

* Remove the unexisted sensor - switch board ambient - from platform.json

Signed-off-by: Stephen Sun <stephens@nvidia.com>

* Do not report error on receiving unknown status on RJ45 ports

Translate it to disconnect for RJ45 ports
Report error for xSFP ports

Signed-off-by: Stephen Sun <stephens@nvidia.com>

* Add reinit for RJ45 to avoid exception

Signed-off-by: Stephen Sun <stephens@nvidia.com>

Co-authored-by: Stephen Sun <5379172+stephenxs@users.noreply.github.com>
Co-authored-by: Stephen Sun <stephens@nvidia.com>
2022-06-20 19:12:20 -07:00
saksarav-nokia
d42a95ce0b
Updated Nokia device BCM and platform config (#11106) 2022-06-18 10:47:49 -07:00
byu343
c1ba71b251
[Arista] Add ASIC configs for blackhawktd4 (#10885)
Why I did it
Add ASIC configs for blackhawktd4

How to verify it
Verified that 400G ports of 400GBASE-CR8 are up and traffic can pass
2022-06-17 12:50:47 -07:00
Santhosh Kumar T
faecf38417
[DellEMC] S5212F and S5224F 2.0 API changes (#10315)
Why I did it
S5212F - Platform API 2.0 changes
S5224F - Platform API 2.0 changes
How I did it
Implemented the functional API's needed for Platform API 2.0
Added media_settings.json, pcie.yaml, platform.json, system_health_monitoring_config.json files.
How to verify it
Used the API 2.0 test suite to validate the test cases.
2022-06-16 16:50:11 -07:00
byu343
89020f53e4
[Arista] Add support support for 7060dx5_64s and 7060px5_64s (#10888)
Why I did it
This change adds the support for Arista 7060dx5_64s and 7060px5_64s

How I did it
How to verify it
We verified the platform driver is working and the ports are up on 7060dx5_64s and 7060px5_64s.
2022-06-16 09:51:42 -07:00
Samuel Angebault
30bfed92fd
[Arista] Add configuration files for 7050X4-32S platform (#10799)
Add most configuration files for the DCS-7050PX4-32S and DCS-7050DX4-32S.
This review only contains platform configuration files, dataplane ones will follow in future change.

Co-authored-by: Zhi Yuan (Carl) Zhao <zyzhao@arista.com>
2022-06-16 09:42:10 -07:00
zitingguo-ms
e2078627c7
[AN/LT][Fix bug]:enable phy_an_lt_msft attribute on some platforms (#11147) 2022-06-15 17:29:45 -07:00
Kebo Liu
b2bc90e34b
add flag skip_xcvrd_cmis_mgr to skip cmis task on Nvidia platform (#11120)
Signed-off-by: Kebo Liu <kebol@nvidia.com>
2022-06-15 16:33:08 -07:00
arunlk-dell
756de913cb
DellEMC: Initial commit for Z9432F platform (#10640)
Why I did it
Added support for the device Z9432F

How I did it
Implemented the support for the platform Z9432F

Switch Vendor: DellEMC
Switch SKU: Z9432F-ON
ASIC Vendor: Broadcom
SONiC Image: sonic-broadcom.bin
2022-06-15 09:39:41 -07:00
Jon Goldberg
b655cd49a3
[Nokia ixs7215] change var/log size to 4GB (#11122)
This makes use of #11121 to add support for configuration of VAR_LOG_SIZE on Nokia IXS7215
2022-06-14 08:57:33 -07:00
Richard.Yu
356b51f4d6
[Tunnel PFC][Fix bug] Fix bug and Tests for adding property 'sai_remap_prio_on_tnl_egress' (#11027)
* [Tunnel PFC] Tests for adding property 'sai_remap_prio_on_tnl_egress'

Add tests for adding property 'sai_remap_prio_on_tnl_egress', this
property should only be added in dual tor environment.

Test done:
Run test test_j2files.py

Co-authored-by: richardyu <richardyu@contoso.com>
2022-06-10 11:14:45 -07:00
Kebo Liu
a3895c3116
[Mellanox] Update SN2201 sai profile and platform reboot script (#10978)
- Why I did it
1. SN2201 sai profile needs to be updated according to the latest hardware.
2. In the reboot script, need to use the common symbol link of the power_cycle sysfs instead of directly accessing it due to SN2201 sysfs is different than other platforms.
3. echo 1 > $SYSFS_PWR_CYCLE will trigger the reboot immediately, the following sleep 3 and echo 0 > $SYSFS_PWR_CYCLE will never be executed, can be removed.

- How I did it
1. Replace the SN2201 sai profile with the latest one.
2. In the platform_reboot script, replace the direct sysfs path with the symbol link path.
3. Remove the redundant code from platform_reboot

- How to verify it
Perform reboot on all the Nvidia platforms, and check all can be rebooted successfully.

Signed-off-by: Kebo Liu <kebol@nvidia.com>
2022-06-07 15:05:54 +03:00
Neetha John
453504f421
[qos]: Adjust 7260 buffer sizes to accomodate extra lossless queues (#11018)
Why I did it
As part of PCBB changes, we need to enable 2 extra lossless queues. The changes in this PR are done to adjust only the reserved sizes on Th2 for the additional 2 lossless queues
Calculations are done based on 40 downlinks for T1 and 16 uplinks for dual ToR

How to verify it
Verified that the rendering works fine on Th2 dut
Unit tests have been updated to reflect the modified buffer sizes when pcbb is enabled. There are existing testcases that will test the original buffer sizes when pcbb is disabled. With these changes, was able to build sonic-config-engine wheel successfully

Signed-off-by: Neetha John <nejo@microsoft.com>
2022-06-05 22:20:26 -07:00
Richard.Yu
a6c9e195df
[Tunnel PFC] Add property for tunnel PFC (#10962)
* [Tunnel PFC] Add property for tunnel PFC

Replace the config.bcm file with j2 template file
- Add 'sai_remap_prio_on_tnl_egress=1' property when device metadata local
- Host subtype is 'dualtor'
- Change sai.profile foe the new config.bcm.j2
2022-06-05 08:08:36 -07:00
bingwang-ms
1cc602c6af
Add two extra lossless queues for bounced back traffic (#10496)
Signed-off-by: bingwang <bingwang@microsoft.com>

Why I did it
This PR is to add two extra lossless queues for bounced back traffic.
HLD sonic-net/SONiC#950

SKUs include
Arista-7050CX3-32S-C32
Arista-7050CX3-32S-D48C8
Arista-7260CX3-D108C8
Arista-7260CX3-C64
Arista-7260CX3-Q64

How I did it
Update the buffers.json.j2 template and buffers_config.j2 template to generate new BUFFER_QUEUE table.

For T1 devices, queue 2 and queue 6 are set as lossless queues on T0 facing ports.
For T0 devices, queue 2 and queue 6 are set as lossless queues on T1 facing ports.
Queue 7 is added as a new lossy queue as DSCP 48 is mapped to TC 7, and then mapped into Queue 7

How to verify it
Verified by UT
Verified by coping the new template and generate buffer config with sonic-cfggen
2022-06-02 13:03:27 -07:00
bingwang-ms
0c9bbee735
Update qos template to support SYSTEM_DEFAULT table (#10936)
* Update qos template to support SYSTEM_DEFAULT table

Signed-off-by: bingwang <wang.bing@microsoft.com>
2022-06-02 21:48:57 +08:00
Samuel Angebault
912923f47b
[Arista] Update supervisor configurations (#10913)
* Removed unused default_config.json

* Remove asic.conf file from HW SKUs directories as they are not used by upstream code

* Enable dynamic PCI ID identification on Otterlake2

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-05-30 13:34:55 -07:00
Taylor Cai
11f0bffe13
[device/celestica]:Fix failed test case of Haliburton snmp (#10844) 2022-05-26 00:06:50 +08:00
abdosi
0285bfe42e
[chassis] Fix issues regarding database service failure handling and mid-plane connectivity for namespace. (#10500)
What/Why I did:

Issue1: By setting up of ipvlan interface in interface-config.sh we are not tolerant to failures. Reason being interface-config.service is one-shot and do not have restart capability. 

Scenario: For example if let's say database service goes in fail state  then interface-services also gets failed because of dependency check but later database service gets restart but interface service will remain in stuck state and the ipvlan interface nevers get created.

Solution: Moved all the logic in database service from interface-config service which looks more align logically also since the namespace is created here and all the network setting (sysctl) are happening here.With this if database starts we recreate the interface.

Issue 2: Use of IPVLAN vs MACVLAN

Currently we are using ipvlan mode.  However above failure scenario is not handle correctly by ipvlan mode. Once the ipvlan interface is created and ip address assign to it and if we restart interface-config or database (new PR) service Linux Kernel gives error "Error: Address already assigned to an ipvlan device."  based on this:https://github.com/torvalds/linux/blob/master/drivers/net/ipvlan/ipvlan_main.c#L978Reason being if we do not do cleanup of ip address assignment (need to be unique for IPVLAN)  it remains in Kernel Database and never goes to free pool even though namespace is deleted. 

Solution: Considering this hard dependency of unique ip macvlan mode is better for us and since everything is managed by Linux Kernel and no dependency for on user configured IP address.

Issue3: Namespace database Service do not check reachability to Supervisor Redis Chassis   Server.

Currently there is no explicit check as we never do Redis PING from namespace to Supervisor Redis Chassis  Server. With this check it's possible we will start database and all other docker even though there is no connectivity and will hit the error/failure late in cycle

Solution: Added explicit PING from namespace that will check this reachability.

Issue 4:flushdb give exception when trying to accces Chassis Server DB over Unix Sokcet.

Solution: Handle gracefully via try..except and log the message.
2022-05-24 16:54:12 -07:00
jerseyang
c92bfe0728
Add belgite support (#9511)
Why I did it
add celestica belgite platform

How I did it
add belgite platform in celestica

Co-authored-by: nicwu-cel <nicwu@celestica.com>
Co-authored-by: anjian <anjian@celestica.com>
Co-authored-by: sandycelestica <sandyli@celestica.com>
2022-05-23 18:45:37 -07:00
Song Yuan
b23ad6748a
[Arista] Add QOS and buffer profiles for SKU Arista-7800R3-48CQM2-C48 (#10752)
* Add QOS and buffer profiles for Arista SKU.

* Add unit test for SKU Arista-7800R3-48CQM2-C48.
2022-05-23 13:50:04 -07:00
Maxime Lorrillere
392899682f
[Arista] Add support for Wolverine linecards (#8887)
Add support for WolverineQCpu, WolverineQCpuMs, WolverineQCpuBk, WolverineQCpuBkMs

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-05-20 14:11:06 -07:00
Marty Y. Lok
937bf09c92
{nokia] Update Nokia IXR7250e supervisor card device data (#10595)
Signed-off-by: mlok <marty.lok@nokia.com>
2022-05-19 11:38:34 -07:00
Vivek R
5ea244cac8
Removed platform specific reboot files for mellanox simx platforms (#10806)
- Why I did it
Platform_reboot files for simx doesn't do aything different apart from calling /sbin/reboot. which is anyway done in the /usr/local/bin/reboot script i.e. the parent script which calls the platform specific reboot scripts if present.

Moreover, /sbin/reboot invoked in the platform specific reboot script is a non-blocking call and thus it returns back to the original script (although /sbin/reboot does it job in the background) and we see messages like this.

Signed-off-by: Vivek Reddy Karri <vkarri@nvidia.com>
2022-05-14 15:20:57 +03:00