Commit Graph

10 Commits

Author SHA1 Message Date
arista-nwolfe
1dea6e4627
[202211] Cherry-picked commits from PR13967 for 202211 (#14791)
* Added recycle ports required for egress mirroring

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>

* Added missing mirror recycle ports for jr2-a7280cr3

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>

---------

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>
2023-06-22 08:13:42 -07:00
mssonicbld
7b61e894ac
sonic-buildimage Remove unused SAT port from arista configs. (#14167) (#14333) 2023-03-19 23:08:48 +08:00
kenneth-arista
67610d7e4f [device/arista] Reduce SDK stat polling freq in DNX devices (#13429)
Eariler the SDK stat polling was erroneously set to once every msec
which is far more frequent than required by SWSS. The new setting, which
is consistent with other vendor SKUs, is once a second. The net result
is reduced CPU MHz by syncd.
2023-02-11 02:38:01 +08:00
kenneth-arista
e3790d3044 [device/arista] Disabled polled_irq_mode for DNX SKUs (#13349)
Disabled polled_irq_mode for all Arista DNX devices as this mode
leads to excessive use of the CPU via an unneeded interrupt
polling thread.
2023-02-04 10:48:10 +08:00
vmittal-msft
cca17ce104
Updated config files to disable DLR_INIT capability (#12401) 2022-10-18 10:13:07 -07:00
kenneth-arista
a4b9838231
[Arista] Enable larger number of LAGs on 7800 LCs (#11070)
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.

Why I did it
The SOC property changes are necessary to match #10519 which increases the number of system LAG IDs to 1024.

Description for the changelog
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.
2022-07-06 14:42:45 -07:00
arista-nwolfe
19dcfd3328
Setting the soc property for num_sa_per_sc on macsec encrypt and decrypt (#11166)
* Setting the soc property for num_sa_per_sc on macsec encrypt and decrypt
* Changed decrypt from 2 to 4 to match broadcom's recommendations
2022-06-27 12:53:57 -07:00
vmittal-msft
981454767d
Updated Chassis MMU settings for 40G/100G/400G line cards (#11108)
* Updated Chassis MMU settings for 40G/100G/400G line cards
2022-06-23 10:03:59 -07:00
Sambath Kumar Balasubramanian
699c4e5bbf
[chassis][voq]Update bcm config file system_ref_core_clock_khz param for j2cplus linecards (#11212)
Update the bcm config file system_ref_core_clock_khz param to handlesystems with J2cplus linecards.

We need system_ref_core_clock_khz to be set to 1600000 for supporting j2 and j2cplus linecards on the same chassis.
2022-06-23 08:03:08 -07:00
Maxime Lorrillere
392899682f
[Arista] Add support for Wolverine linecards (#8887)
Add support for WolverineQCpu, WolverineQCpuMs, WolverineQCpuBk, WolverineQCpuBkMs

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-05-20 14:11:06 -07:00