Commit Graph

18 Commits

Author SHA1 Message Date
arista-nwolfe
1dea6e4627
[202211] Cherry-picked commits from PR13967 for 202211 (#14791)
* Added recycle ports required for egress mirroring

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>

* Added missing mirror recycle ports for jr2-a7280cr3

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>

---------

Signed-off-by: Nathan Wolfe <nwolfe@arista.com>
2023-06-22 08:13:42 -07:00
Samuel Angebault
f394121903 [Arista] Add missing platform_components.json (#14067)
Provide platform-components.json for Clearwater2 and Wolverine

These files are needed for fwutil platform sonic-mgmt tests to pass.

Fix PikeZ platform_components.json

Co-authored-by: Patrick MacArthur <pmacarthur@arista.com>
Co-authored-by: Andy Wong <andywong@arista.com>
2023-03-20 20:54:49 +08:00
mssonicbld
7b61e894ac
sonic-buildimage Remove unused SAT port from arista configs. (#14167) (#14333) 2023-03-19 23:08:48 +08:00
Song Yuan
09a3f922fb Add QOS profiles for Arista SKUs (#13829) 2023-03-19 22:33:05 +08:00
Patrick MacArthur
ff5605ae00
fix platform.json on Wolverine for thermal sensors (#13984)
Why I did it
Manual rebase of PR #13524 to 202211 branch.

How I did it
See PR #13524
2023-02-28 08:54:01 +08:00
kenneth-arista
67610d7e4f [device/arista] Reduce SDK stat polling freq in DNX devices (#13429)
Eariler the SDK stat polling was erroneously set to once every msec
which is far more frequent than required by SWSS. The new setting, which
is consistent with other vendor SKUs, is once a second. The net result
is reduced CPU MHz by syncd.
2023-02-11 02:38:01 +08:00
kenneth-arista
e3790d3044 [device/arista] Disabled polled_irq_mode for DNX SKUs (#13349)
Disabled polled_irq_mode for all Arista DNX devices as this mode
leads to excessive use of the CPU via an unneeded interrupt
polling thread.
2023-02-04 10:48:10 +08:00
Bohan Yang
9b7a04dc0e [Arista]Add media_settings.json for x86_64-arista_7800r3a_36d2_lc (#12444)
Why I did it
TX FIR tuning should be done based on the type of inserted transceiver

How I did it
Add media_settings.json which contains the tuning data for 100G optic and 400G optic.

How to verify it
Tested against x86_64-arista_7800r3a_36d2_lc
2022-12-10 10:33:21 +08:00
judyjoseph
c259c996b4
Use the macsec_enabled flag in platform to enable macsec feature state (#11998)
* Use the macsec_enabled flag in platform to enable macesc feature state
* Add macsec supported metadata in DEVICE_RUNTIME_METADATA
2022-11-08 11:03:38 -08:00
vmittal-msft
cca17ce104
Updated config files to disable DLR_INIT capability (#12401) 2022-10-18 10:13:07 -07:00
Sambath Kumar Balasubramanian
7ba1d25757
Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards. (#11813)
Add 36 port 100g sku for x86_64-arista_7800r3a_36d series of linecards.
2022-10-17 11:15:19 -07:00
Bohan Yang
fad4034000
Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards. (#11872)
Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards.
2022-10-13 20:36:44 -07:00
kenneth-arista
a4b9838231
[Arista] Enable larger number of LAGs on 7800 LCs (#11070)
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.

Why I did it
The SOC property changes are necessary to match #10519 which increases the number of system LAG IDs to 1024.

Description for the changelog
For 7800 LCs, set LAG mode to support 1024 number of 16-member system
LAGs.
2022-07-06 14:42:45 -07:00
Samuel Angebault
7b98cf35c3
[Arista] Update configurations for 7800R3A-36D2 (#10987)
Why I did it
This linecard runs in multi-asic mode and therefore needs the use_pcie_id_chassis file to work properly.
The default_sku file was also missing which would break the boot when no minigraph is provided.

Description for the changelog
Add missing default_sku and use_pci_id_chassis configs for 7800R3A-36D2
2022-07-05 18:57:52 -07:00
arista-nwolfe
19dcfd3328
Setting the soc property for num_sa_per_sc on macsec encrypt and decrypt (#11166)
* Setting the soc property for num_sa_per_sc on macsec encrypt and decrypt
* Changed decrypt from 2 to 4 to match broadcom's recommendations
2022-06-27 12:53:57 -07:00
vmittal-msft
981454767d
Updated Chassis MMU settings for 40G/100G/400G line cards (#11108)
* Updated Chassis MMU settings for 40G/100G/400G line cards
2022-06-23 10:03:59 -07:00
Sambath Kumar Balasubramanian
699c4e5bbf
[chassis][voq]Update bcm config file system_ref_core_clock_khz param for j2cplus linecards (#11212)
Update the bcm config file system_ref_core_clock_khz param to handlesystems with J2cplus linecards.

We need system_ref_core_clock_khz to be set to 1600000 for supporting j2 and j2cplus linecards on the same chassis.
2022-06-23 08:03:08 -07:00
Maxime Lorrillere
392899682f
[Arista] Add support for Wolverine linecards (#8887)
Add support for WolverineQCpu, WolverineQCpuMs, WolverineQCpuBk, WolverineQCpuBkMs

Co-authored-by: Maxime Lorrillere <mlorrillere@arista.com>
2022-05-20 14:11:06 -07:00