Commit Graph

8 Commits

Author SHA1 Message Date
gechiang
baa00e6969
[202012] Disable ALPM distributed hitbit thread that is used for debug purpose only but interfered with Other functional operations (#9190)
This is to address an issue where it was observed that SAI operations sometime make take a very long to time complete (over 45ms). It was determined that the ALPM distributed thread was causing this issue.
The fix is to disable this debug thread that has no functional purpose.

Preliminary tests looks fine. BGP neighbors were all up with proper routes programmed
interfaces are all up
Manually ran the fib test cases on 7050CX3 (TD3), TD2, TH, TH2, and TH3 based platforms and
thy all passed.
2021-11-08 11:50:44 -08:00
gechiang
8915e488b7
[202012] BRCM Disable ACL Drop counted towards interface RX_DRP counters (#8383)
* [202012] BRCM Disable ACL Drop counted towards interface RX_DRP counters
2021-08-11 09:10:17 -07:00
Joe LeVeque
deb9e67838
[202012] Add SOC property to enable AN/LT on some platforms (#7547)
* [202012] Add SOC property to enable AN/LT on some platforms

Why I did it
To enable autonegotiation/link training on some Broadcom-based platforms (Arista 7060CX, 7260CX3, 7050cx3, Celestica DX010)

How I did it
Add appropriate SOC property for enabling the feature to the Broadcom config files of appropriate platforms
Also convert line endings to UNIX format for one Celestica file

* Add 'phy_an_lt_msft' to BCM config file permitted list
2021-05-06 22:21:43 -07:00
Ying Xie
1ba583cb46
[TD3] add dummy MMU configuration for Arista-7050CX3-32S-D48C8 (#5950)
Need A mmu configuration to get the device going without generating lots of warnings.

Similar to dummy MMU configuration for Arista-7050CX3-32S-C32, this configuration will need to be updated with correct numbers. This MMU configuration is copied from 7060 comparable hwsku.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2020-11-17 19:01:39 -08:00
abdosi
a6a10f05b7
In SAI 3.5 by default we are supporting 256 Group with 64 Memeber each. (#5400)
However in SAI 3.7 default behaviout got changes to 128 Group and 128
    Memeber each.

    This change is to make sure we are using same ECMP Group/Memeber Per
    Group for 3.7 also so that behaviour is consistent.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2020-09-22 11:21:12 -07:00
abdosi
b6efb49817
Update bcm soc property bcm_num_cos from 8 to 10 (#5314)
as needed by SAI 3.7 and above. Without this change
Warmboot fails from 3.5 to 3.7 as Braodcoam Datastructure
gets corrupted after warm-boot.

Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
2020-09-04 07:40:17 -07:00
Wenda Ni
7b0a5ba6ae Remove the divide by 4 operation to the under the hood SAI (#1532)
* Remove the divide by 4 operation to the under the hood SAI

This is to avoid the need and thus the confusion for application program to know
the mmu internal architecture

This change must have support from SAI change to reach the correct
config

Signed-off-by: Wenda <wenni@microsoft.com>

* Relegate the divide by 4 operation to the under the hood SAI for egress
lossless pool

Extend to 7060 and 6100

Signed-off-by: Wenda <wenni@microsoft.com>

* Add more TH/TH2 hwskus

Signed-off-by: Wenda Ni <wenni@microsoft.com>

* Update config test

Signed-off-by: Wenda Ni <wenni@microsoft.com>

* Add TH2 ingress lossy profile

Signed-off-by: Wenda Ni <wenni@microsoft.com>

* Move the divide by 4 operation to SAI internal

Signed-off-by: Wenda Ni <wenni@microsoft.com>

* [bcm SAI] Upgrade Broadcom SAI to version 3.5.3.1-15

- Broadcom SAI 3.5 GA release 20190924.

Signed-off-by: Ying Xie <ying.xie@microsoft.com>
2019-09-25 15:57:07 -07:00
Michel Moriniaux
62e994d8ec [HWSKU] add Arista-7060CX-32S-T96C8 and Arista-7060CX-32S-Q24C8 (#2617)
* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU

Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>

* [HWSKU] Added Arista-7060CX-32S-T96C8 HWSKU

Added the bcm config files for a 96x25G+8x100G ToR

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>

* [HWSKU] Added Arista-7060CX-32S-Q24C8 HWSKU

Added an Arista HWSKU with 24x40G + 8x100G ports
The ports are distributed along core lines

Signed-off-by: Michel Moriniaux <m.moriniaux@criteo.com>
2019-03-15 09:45:17 -07:00