sonic-buildimage/device/mellanox/x86_64-mlnx_msn3800-r0/Mellanox-SN3800-D112C8/pg_profile_lookup.ini

#  PG lossless profiles.
# speed cable  size   xon    xoff   threshold
  10000    5m 19456  19456  25600          0
  25000    5m 19456  19456  28672          0
  40000    5m 19456  19456  30720          0
  50000    5m 19456  19456  32768          0
 100000    5m 19456  19456  40960          0
  10000   40m 19456  19456  26624          0
  25000   40m 19456  19456  30720          0
  40000   40m 19456  19456  33792          0
  50000   40m 19456  19456  36864          0
 100000   40m 19456  19456  48128          0
  10000  300m 19456  19456  31744          0
  25000  300m 19456  19456  44032          0
  40000  300m 19456  19456  55296          0
  50000  300m 19456  19456  63488          0
 100000  300m 19456  19456 102400          0
  10000 2000m 19456  19456  33792          0
  25000 2000m 19456  19456  65536          0
  40000 2000m 19456  19456  97280          0
  50000 2000m 19456  19456 118784          0
 100000 2000m 19456  19456 225280          0
Support single ingress pool for MSFT SKUs and optimize headroom calculation (#5194) This is to backport the #4886 to 201911 Calculate pool size in t1 as 24 * downlink port + 8 * uplink port - Take both port and peer MTU into account when calculating headroom - Worst case factor is decreased to 50% - Mellanox-SN2700-C28D8 t0, assume 48 * 50G/5m + 8 * 100G/40m ports - Mellanox-SN2700 (C32) - t0: 16 * 100G/5m + 16 * 100G/40m - t1: 16 * 100G/40m + 16 * 100G/300m Signed-off-by: Stephen Sun <stephens@nvidia.com> 2020-08-15 09:52:28 -05:00			`# PG lossless profiles.`
			`# speed cable size xon xoff threshold`
[Mellanox] [201911] Support shared headroom pool (#5908) 2021-01-07 01:20:22 -06:00			`10000 5m 19456 19456 25600 0`
			`25000 5m 19456 19456 28672 0`
			`40000 5m 19456 19456 30720 0`
			`50000 5m 19456 19456 32768 0`
			`100000 5m 19456 19456 40960 0`
			`10000 40m 19456 19456 26624 0`
			`25000 40m 19456 19456 30720 0`
			`40000 40m 19456 19456 33792 0`
			`50000 40m 19456 19456 36864 0`
			`100000 40m 19456 19456 48128 0`
			`10000 300m 19456 19456 31744 0`
			`25000 300m 19456 19456 44032 0`
			`40000 300m 19456 19456 55296 0`
			`50000 300m 19456 19456 63488 0`
[Mellanox][201911] Support buffer configuration for 2km cable (#7338) #### Why I did it 1. Update pg_profile_lookup.ini with 2000m cable supported 2. Update buffer configuration for t1 with uplink cable 2000m - For SN3800 platform: - C64: - t0: 32 100G down links and 32 100G up links. - t1: 56 100G down links and 8 100G up links with 2 km cable. - D112C8: 112 50G down links and 8 100G up links. - D24C52: 24 50G down links, 20 100G down links, and 32 100G up links. - D28C50: 28 50G down links, 18 100G down links, and 32 100G up links. - For SN2700 platform: - D48C8: 48 50G down links and 8 100G up links - C32: - t0: 16 100G down links and 16 100G up links. - t1: 24 100G down links and 8 100G up links with 2 km cable. Signed-off-by: Stephen Sun <stephens@nvidia.com> #### How I did it #### How to verify it Run QoS regression test 2021-05-30 22:03:16 -05:00			`100000 300m 19456 19456 102400 0`
			`10000 2000m 19456 19456 33792 0`
			`25000 2000m 19456 19456 65536 0`
			`40000 2000m 19456 19456 97280 0`
			`50000 2000m 19456 19456 118784 0`
			`100000 2000m 19456 19456 225280 0`