147 lines
4.4 KiB
C
147 lines
4.4 KiB
C
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/*******************************************************************************
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Barefoot Networks Switch ASIC Linux driver
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Copyright(c) 2015 - 2019 Barefoot Networks, Inc.
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This program is free software; you can redistribute it and/or modify it
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under the terms and conditions of the GNU General Public License,
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version 2, as published by the Free Software Foundation.
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This program is distributed in the hope it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc.,
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51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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The full GNU General Public License is included in this distribution in
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the file called "COPYING".
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Contact Information:
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info@barefootnetworks.com
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Barefoot Networks, 4750 Patrick Henry Drive, Santa Clara CA 95054
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*******************************************************************************/
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#ifndef _BF_KDRV_H_
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#define _BF_KDRV_H_
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#include <linux/pci.h>
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#include <linux/msi.h>
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#include <linux/version.h>
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#ifndef phys_addr_t
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typedef uint64_t phys_addr_t;
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#endif
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#define PCI_VENDOR_ID_BF 0x1d1c
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#define TOFINO_DEV_ID_A0 0x01
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#define TOFINO_DEV_ID_B0 0x10
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#define TOFINO2_DEV_ID_A0 0x0100
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#define TOFINO2_DEV_ID_A00 0x0000
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#define TOFINO2_DEV_ID_B0 0x0110
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#ifndef PCI_MSIX_ENTRY_SIZE
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#define PCI_MSIX_ENTRY_SIZE 16
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#define PCI_MSIX_ENTRY_LOWER_ADDR 0
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#define PCI_MSIX_ENTRY_UPPER_ADDR 4
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#define PCI_MSIX_ENTRY_DATA 8
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#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
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#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
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#endif
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#define BF_CLASS_NAME "bf"
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#define BF_MAX_DEVICE_CNT 256
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#define BF_INTR_MODE_NONE_NAME "none"
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#define BF_INTR_MODE_LEGACY_NAME "legacy"
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#define BF_INTR_MODE_MSI_NAME "msi"
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#define BF_INTR_MODE_MSIX_NAME "msix"
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#define BF_MAX_BAR_MAPS 6
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#define BF_MSIX_ENTRY_CNT 32 /* 512 for tofino-1 */
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#define BF_MSI_ENTRY_CNT 2
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#define BF_MSI_INT_TBUS 1
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#define BF_TBUS_MSIX_INDEX_INVALID (0)
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#define BF_TBUS_MSIX_BASE_INDEX_TOF1 (32)
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/* Tofino generation type */
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typedef enum {
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BF_TOFINO_NONE = 0,
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BF_TOFINO_1,
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BF_TOFINO_2,
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} bf_tof_type;
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/* device memory */
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struct bf_dev_mem {
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const char *name;
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phys_addr_t addr;
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resource_size_t size;
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void __iomem *internal_addr;
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};
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struct bf_listener {
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struct bf_pci_dev *bfdev;
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s32 event_count[BF_MSIX_ENTRY_CNT];
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int minor;
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struct bf_listener *next;
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};
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/* device information */
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struct bf_dev_info {
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struct module *owner;
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struct device *dev;
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int minor;
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atomic_t event[BF_MSIX_ENTRY_CNT];
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wait_queue_head_t wait;
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const char *version;
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struct bf_dev_mem mem[BF_MAX_BAR_MAPS];
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struct msix_entry *msix_entries;
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long irq; /* first irq vector */
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int num_irq; /* number of irq vectors */
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unsigned long irq_flags; /* sharable ?? */
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uint16_t pci_dev_id; /* generation type of BF ASIC */
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bf_tof_type tof_type; /* Tofino generation type */
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/* msix index assigned to tbus MSIX for Tofino-2 only */
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int tbus_msix_ind[BF_TBUS_MSIX_INDICES_MAX];
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int tbus_msix_map_enable;
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int pci_error_state; /* was there a pci bus error */
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};
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/* cookie to be passed to IRQ handler, useful especially with MSIX */
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struct bf_int_vector {
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struct bf_pci_dev *bf_dev;
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int int_vec_offset;
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};
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/**
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* A structure describing the private information for a BF pcie device.
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*/
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struct bf_pci_dev {
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struct bf_dev_info info;
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struct pci_dev *pdev;
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enum bf_intr_mode mode;
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u8 instance;
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char name[16];
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struct bf_int_vector bf_int_vec[BF_MSIX_ENTRY_CNT];
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struct bf_listener *
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listener_head; /* head of a singly linked list of listeners */
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void *adapter_ptr; /* pkt processing adapter */
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};
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/* TBD: Need to build with CONFIG_PCI_MSI */
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#if LINUX_VERSION_CODE < KERNEL_VERSION(3, 14, 0)
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#if defined(RHEL_RELEASE_CODE)
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#else
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extern int pci_enable_msi_block(struct pci_dev *dev, unsigned int nvec);
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#endif /* defined(RHEL_RELEASE_CODE) */
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extern int pci_enable_msix(struct pci_dev *dev, struct msix_entry *entries, int nvec);
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#else
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extern int pci_enable_msi_range(struct pci_dev *dev, int minvec, int maxvec);
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extern int pci_enable_msix_range(struct pci_dev *dev,
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struct msix_entry *entries,
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int minvec,
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int maxvec);
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#endif
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#endif /* _BF_KDRV_H_ */
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