252 lines
6.7 KiB
C
Executable File
252 lines
6.7 KiB
C
Executable File
/* Copyright (C) 2020 MediaTek, Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of version 2 of the GNU General Public
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* License as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* version 2 along with this program.
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*/
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/* FILE NAME: osal_mdc.h
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* PURPOSE:
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* 1. Provide device operate from AML interface
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* NOTES:
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*
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*/
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#ifndef OSAL_MDC_H
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#define OSAL_MDC_H
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/* INCLUDE FILE DECLARATIONS */
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#include <nps_types.h>
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#include <aml.h>
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#define OSAL_MDC_DRIVER_NAME "nps_dev"
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#define OSAL_MDC_DRIVER_MISC_MAJOR_NUM (10)
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#define OSAL_MDC_DRIVER_MISC_MINOR_NUM (250)
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#define OSAL_MDC_PCI_BUS_WIDTH (4)
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#define OSAL_MDC_DMA_LIST_SZ_UNLIMITED (0)
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#define OSAL_MDC_DMA_LIST_NAME "RSRV_DMA"
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#define OSAL_MDC_DMA_SEMAPHORE_NAME "DMALIST"
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/* NAMING CONSTANT DECLARATIONS
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*/
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/* linked list node */
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#if defined(NPS_LINUX_KERNEL_MODE)
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typedef struct OSAL_MDC_LIST_NODE_S
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{
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void *ptr_data; /* node data */
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struct OSAL_MDC_LIST_NODE_S *ptr_next; /* point to next link node */
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struct OSAL_MDC_LIST_NODE_S *ptr_prev; /* point to previous link node */
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} OSAL_MDC_LIST_NODE_T;
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/* linked list head */
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typedef struct OSAL_MDC_LIST_S
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{
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OSAL_MDC_LIST_NODE_T *ptr_head_node; /* linked list head node */
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OSAL_MDC_LIST_NODE_T *ptr_tail_node; /* linked list tail node */
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UI32_T capacity; /* max count of nodes in list
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* size=0: the capacity is unlimited.
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* size>0: the capacity is limited.
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*/
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UI32_T node_cnt; /* the count of nodes in the list */
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} OSAL_MDC_LIST_T;
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#endif /* End of defined(NPS_LINUX_KERNEL_MODE) */
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typedef struct
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{
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NPS_ADDR_T phy_addr;
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void *ptr_virt_addr;
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NPS_ADDR_T size;
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#if defined(NPS_EN_DMA_RESERVED)
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BOOL_T available;
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#endif
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} OSAL_MDC_DMA_NODE_T;
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typedef struct
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{
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#if defined(NPS_EN_DMA_RESERVED)
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void *ptr_rsrv_virt_addr;
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NPS_ADDR_T rsrv_phy_addr;
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NPS_ADDR_T rsrv_size;
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#else
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struct device *ptr_dma_dev; /* for allocate/free system memory */
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#endif
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void *ptr_dma_list; /* the type should be casted again when use */
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NPS_SEMAPHORE_ID_T sema;
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} OSAL_MDC_DMA_INFO_T;
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#if defined(NPS_LINUX_USER_MODE)
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/* Data type of IOCTL argument for DMA management */
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typedef struct
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{
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#if defined(NPS_EN_DMA_RESERVED)
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NPS_ADDR_T rsrv_dma_phy_addr; /* information of reserved memory */
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NPS_ADDR_T rsrv_dma_size;
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#else
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NPS_ADDR_T phy_addr; /* information of system memory */
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NPS_ADDR_T size;
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#endif
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} OSAL_MDC_IOCTL_DMA_DATA_T;
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/* Data type of IOCTL argument for device initialization */
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#pragma pack (push,1)
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typedef struct
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{
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AML_DEV_ID_T id[NPS_CFG_MAXIMUM_CHIPS_PER_SYSTEM];
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NPS_ADDR_T pci_mmio_phy_start[NPS_CFG_MAXIMUM_CHIPS_PER_SYSTEM];
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NPS_ADDR_T pci_mmio_size[NPS_CFG_MAXIMUM_CHIPS_PER_SYSTEM];
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UI32_T dev_num;
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} OSAL_MDC_IOCTL_DEV_DATA_T;
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#pragma pack (pop)
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typedef enum
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{
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OSAL_MDC_IOCTL_ACCESS_READ = 0,
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OSAL_MDC_IOCTL_ACCESS_WRITE,
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OSAL_MDC_IOCTL_ACCESS_READ_WRITE,
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OSAL_MDC_IOCTL_ACCESS_NONE,
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OSAL_MDC_IOCTL_ACCESS_LAST
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} OSAL_MDC_IOCTL_ACCESS_T;
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typedef enum
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{
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OSAL_MDC_IOCTL_TYPE_MDC_INIT_DEV = 0,
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OSAL_MDC_IOCTL_TYPE_MDC_DEINIT_DEV,
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OSAL_MDC_IOCTL_TYPE_MDC_INIT_RSRV_DMA_MEM,
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OSAL_MDC_IOCTL_TYPE_MDC_DEINIT_RSRV_DMA_MEM,
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OSAL_MDC_IOCTL_TYPE_MDC_ALLOC_SYS_DMA_MEM,
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OSAL_MDC_IOCTL_TYPE_MDC_FREE_SYS_DMA_MEM,
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OSAL_MDC_IOCTL_TYPE_MDC_CONNECT_ISR,
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OSAL_MDC_IOCTL_TYPE_MDC_DISCONNECT_ISR,
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OSAL_MDC_IOCTL_TYPE_MDC_SAVE_PCI_CONFIG,
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OSAL_MDC_IOCTL_TYPE_MDC_RESTORE_PCI_CONFIG,
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OSAL_MDC_IOCTL_TYPE_LAST
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} OSAL_MDC_IOCTL_TYPE_T;
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typedef union
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{
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UI32_T value;
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struct
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{
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UI32_T access : 2; /* 0:read, 1:write, 2:read and write, 3:none */
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UI32_T unit : 6; /* Maximum unit number is 64. */
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UI32_T size :14; /* Maximum IOCTL data size is 16KB. */
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UI32_T type :10; /* Maximum 1024 IOCTL types */
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} field;
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} OSAL_MDC_IOCTL_CMD_T;
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typedef NPS_ERROR_NO_T
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(*OSAL_MDC_IOCTL_CALLBACK_FUNC_T)(
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const UI32_T unit,
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void *ptr_data);
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#endif /* End of NPS_LINUX_USER_MODE */
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/* MACRO FUNCTION DECLARATIONS
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*/
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/* DATA TYPE DECLARATIONS
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*/
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/* EXPORTED SUBPROGRAM SPECIFICATIONS
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*/
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NPS_ERROR_NO_T
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osal_mdc_readPciReg(
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const UI32_T unit,
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const UI32_T offset,
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UI32_T *ptr_data,
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const UI32_T len);
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NPS_ERROR_NO_T
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osal_mdc_writePciReg(
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const UI32_T unit,
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const UI32_T offset,
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const UI32_T *ptr_data,
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const UI32_T len);
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NPS_ERROR_NO_T
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osal_mdc_initDevice(
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AML_DEV_T *ptr_dev_list,
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UI32_T *ptr_dev_num);
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NPS_ERROR_NO_T
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osal_mdc_deinitDevice(void);
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NPS_ERROR_NO_T
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osal_mdc_initDmaMem(void);
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NPS_ERROR_NO_T
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osal_mdc_deinitDmaMem(void);
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void *
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osal_mdc_allocDmaMem(
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const UI32_T size);
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NPS_ERROR_NO_T
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osal_mdc_freeDmaMem(
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void *ptr_virt_addr);
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NPS_ERROR_NO_T
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osal_mdc_convertVirtToPhy(
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void *ptr_virt_addr,
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NPS_ADDR_T *ptr_phy_addr);
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NPS_ERROR_NO_T
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osal_mdc_convertPhyToVirt(
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const NPS_ADDR_T phy_addr,
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void **pptr_virt_addr);
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NPS_ERROR_NO_T
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osal_mdc_registerIsr(
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const UI32_T unit,
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AML_DEV_ISR_FUNC_T handler,
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void *ptr_cookie);
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NPS_ERROR_NO_T
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osal_mdc_connectIsr(
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const UI32_T unit,
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AML_DEV_ISR_FUNC_T handler,
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AML_DEV_ISR_DATA_T *ptr_cookie);
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NPS_ERROR_NO_T
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osal_mdc_disconnectIsr(
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const UI32_T unit);
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NPS_ERROR_NO_T
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osal_mdc_flushCache(
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void *ptr_virt_addr,
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const UI32_T size);
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NPS_ERROR_NO_T
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osal_mdc_invalidateCache(
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void *ptr_virt_addr,
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const UI32_T size);
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NPS_ERROR_NO_T
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osal_mdc_savePciConfig(
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const UI32_T unit);
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NPS_ERROR_NO_T
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osal_mdc_restorePciConfig(
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const UI32_T unit);
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#endif /* OSAL_MDC_H */
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