e286869b24
- Why I did it 1. Update Mellanox HW-MGMT package to newer version V.7.0030.1011 2. Replace the SONiC PMON Thermal control algorithm with the one inside the HW-MGMT package on all Nvidia platforms 3. Support Spectrum-4 systems - How I did it 1. Update the HW-MGMT package version number and submodule pointer 2. Remove the thermal control algorithm implementation from Mellanox platform API 3. Revise the patch to HW-MGMT package which will disable HW-MGMT from running on SIMX 4. Update the downstream kernel patch list Signed-off-by: Kebo Liu <kebol@nvidia.com>
98 lines
3.8 KiB
Diff
98 lines
3.8 KiB
Diff
From 4eafb2c053cc5935fe826da97fda42abadab5fc1 Mon Sep 17 00:00:00 2001
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From: David Thompson <davthompson@nvidia.com>
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Date: Wed, 11 May 2022 09:52:51 -0400
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Subject: [PATCH backport 5.10 31/63] mlxbf_gige: remove driver-managed
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interrupt counts
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BugLink: https://bugs.launchpad.net/bugs/1979827
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The driver currently has three interrupt counters,
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which are incremented every time each interrupt handler
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executes. These driver-managed counters are not
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necessary as the kernel already has logic that manages
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interrupt counts and exposes them via /proc/interrupts.
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This patch removes the driver-managed counters.
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Signed-off-by: David Thompson <davthompson@nvidia.com>
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Signed-off-by: Asmaa Mnebhi <asmaa@nvidia.com>
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Link: https://lore.kernel.org/r/20220511135251.2989-1-davthompson@nvidia.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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(cherry picked from commit f4826443f4d69d2c97c184952c085caf0936a7b8)
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Signed-off-by: Ike Panhc <ike.pan@canonical.com>
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---
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drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h | 3 ---
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.../ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c | 8 +++-----
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.../net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c | 9 ---------
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3 files changed, 3 insertions(+), 17 deletions(-)
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diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
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index 86826a70f..5fdf9b717 100644
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--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
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+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige.h
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@@ -90,9 +90,6 @@ struct mlxbf_gige {
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dma_addr_t rx_cqe_base_dma;
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u16 tx_pi;
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u16 prev_tx_ci;
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- u64 error_intr_count;
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- u64 rx_intr_count;
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- u64 llu_plu_intr_count;
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struct sk_buff *rx_skb[MLXBF_GIGE_MAX_RXQ_SZ];
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struct sk_buff *tx_skb[MLXBF_GIGE_MAX_TXQ_SZ];
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int error_irq;
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diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c
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index 92b798f8e..af46b0cd7 100644
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--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c
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+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_ethtool.c
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@@ -24,11 +24,9 @@ static void mlxbf_gige_get_regs(struct net_device *netdev,
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regs->version = MLXBF_GIGE_REGS_VERSION;
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/* Read entire MMIO register space and store results
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- * into the provided buffer. Each 64-bit word is converted
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- * to big-endian to make the output more readable.
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- *
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- * NOTE: by design, a read to an offset without an existing
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- * register will be acknowledged and return zero.
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+ * into the provided buffer. By design, a read to an
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+ * offset without an existing register will be
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+ * acknowledged and return zero.
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*/
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memcpy_fromio(p, priv->base, MLXBF_GIGE_MMIO_REG_SZ);
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}
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diff --git a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c
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index c38795be0..5b3519f0c 100644
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--- a/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c
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+++ b/drivers/net/ethernet/mellanox/mlxbf_gige/mlxbf_gige_intr.c
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@@ -17,8 +17,6 @@ static irqreturn_t mlxbf_gige_error_intr(int irq, void *dev_id)
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priv = dev_id;
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- priv->error_intr_count++;
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-
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int_status = readq(priv->base + MLXBF_GIGE_INT_STATUS);
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if (int_status & MLXBF_GIGE_INT_STATUS_HW_ACCESS_ERROR)
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@@ -75,8 +73,6 @@ static irqreturn_t mlxbf_gige_rx_intr(int irq, void *dev_id)
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priv = dev_id;
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- priv->rx_intr_count++;
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-
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/* NOTE: GigE silicon automatically disables "packet rx" interrupt by
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* setting MLXBF_GIGE_INT_MASK bit0 upon triggering the interrupt
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* to the ARM cores. Software needs to re-enable "packet rx"
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@@ -90,11 +86,6 @@ static irqreturn_t mlxbf_gige_rx_intr(int irq, void *dev_id)
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static irqreturn_t mlxbf_gige_llu_plu_intr(int irq, void *dev_id)
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{
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- struct mlxbf_gige *priv;
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-
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- priv = dev_id;
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- priv->llu_plu_intr_count++;
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-
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return IRQ_HANDLED;
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}
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--
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2.20.1
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