08f3b9720b
summary of E530 platfrom: - CPU: CTC5236, arm64 - LAN switch chip set: CENTEC CTC7132 (TsingMa). TsingMa is a purpose built device to address the challenge in the recent network evolution such as Cloud computing. CTC7132 provides 440Gbps I/O bandwidth and 400Gcore bandwidth, the CTC7132 family combines a feature-rich switch core and an embedded ARM A53 CPU Core running at 800MHz/1.2GHz. CTC7132 supports a variety of port configurations, such as QSGMII and USXGMII-M, providing full-rate port capability from 100M to 100G. - device E530-48T4X: 48 * 10/100/1000 Base-T Ports, 4 * 10GE SFP+ Ports. - device E530-24X2C: 24 * 10 GE SFP+ Ports, 2 * 100GE QSFP28 Ports. add new files in three directories: device/centec/arm64-centec_e530_24x2c-r0 device/centec/arm64-centec_e530_48t4x_p-r0 platform/centec-arm64 Co-authored-by: taocy <taocy2@centecnetworks.com> Co-authored-by: Gu Xianghong <gxh2001757@163.com> Co-authored-by: shil <shil@centecnetworks.com>
377 lines
11 KiB
Plaintext
377 lines
11 KiB
Plaintext
/*
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* dts file for Centec CTC5236(TsingMa) SoC
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*
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* (C) Copyright 2004-2017 Centec Networks (suzhou) Co., LTD.
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*
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* Jay Cao <caoj@centecnetworks.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include "arm-gic.h"
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#include "ctc5236-clks.h"
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#include "../pinctrl-ctc/pinctrl-ctc.h"
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/ {
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compatible = "centec,ctc5236";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&cpu0>;
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};
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core1 {
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cpu = <&cpu1>;
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};
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};
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};
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x000>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x0010fff0>;
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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compatible = "arm,cortex-a53", "arm,armv8";
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reg = <0 0x001>;
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enable-method = "spin-table";
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cpu-release-addr = <0 0x0010fff0>;
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};
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};
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gic: interrupt-controller@31201000 {
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compatible = "arm,gic-400";
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#interrupt-cells = <3>;
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interrupt-controller;
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reg = <0x0 0x31201000 0 0x1000>,
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<0x0 0x31202000 0 0x2000>,
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<0x0 0x31204000 0 0x2000>,
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<0x0 0x31206000 0 0x2000>;
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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};
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timer {
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compatible = "arm,armv8-timer";
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interrupt-parent = <&gic>;
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>;
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};
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soc: soc {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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#include "ctc5236-clock.dtsi"
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ocram: sram@00100000 {
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compatible = "mmio-sram";
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reg = <0x0 0x00100000 0x0 0x10000>;
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};
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memory-controller@30600000 {
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compatible = "ctc,ctc5236-ddr-ctrl";
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reg = <0x0 0x30600000 0x0 0x100000>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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};
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sysctrl: sysctrl@33200000 {
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compatible = "ctc,ctc5236-sysctrl", "syscon";
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reg = <0x0 0x33200000 0x0 0x100000>;
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little-endian;
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};
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serial0: serial@33000000 {
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compatible = "arm,pl011","arm,primecell";
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reg = <0x0 0x33000000 0x0 0x1000>;
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interrupts = <GIC_SPI 25 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&uart_clk>, <&sup_clk>;
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clock-names = "uart_clk", "apb_pclk";
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status="disabled";
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};
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serial1: serial@33001000 {
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compatible = "arm,pl011","arm,primecell";
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reg = <0x0 0x33001000 0x0 0x1000>;
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interrupts = <GIC_SPI 26 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&uart_clk>, <&sup_clk>;
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clock-names = "uart_clk", "apb_pclk";
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status="disabled";
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};
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serial2: serial@33002000 {
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compatible = "arm,pl011","arm,primecell";
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reg = <0x0 0x33002000 0x0 0x1000>;
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interrupts = <GIC_SPI 27 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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clocks = <&uart_clk>, <&sup_clk>;
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clock-names = "uart_clk", "apb_pclk";
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status="disabled";
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};
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mdio: mdio@33620000 {
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compatible = "ctc,mdio";
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reg = <0x0 0x33620000 0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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status = "disabled";
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};
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enet0: ethernet@33410000 {
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compatible = "ctc,mac";
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device_type = "network";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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status = "disabled";
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index = <0x00>;
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reg = <0x0 0x33410000 0x0 0x10000>,
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<0x0 0x33400000 0x0 0x10000>;
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interrupts = <GIC_SPI 40 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 41 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 44 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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ctc,sysctrl = <&sysctrl>;
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};
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enet1: ethernet@33420000 {
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compatible = "ctc,mac";
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device_type = "network";
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#address-cells = <2>;
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#size-cells = <2>;
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interrupt-parent = <&gic>;
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status = "disabled";
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index = <0x01>;
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reg = <0x0 0x33420000 0x0 0x10000>,
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<0x0 0x33400000 0x0 0x10000>;
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interrupts = <GIC_SPI 42 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 43 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 44 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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ctc,sysctrl = <&sysctrl>;
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};
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ehci0: usb@30500000 {
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compatible = "ctc-ehci";
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reg = <0x0 0x30500000 0x0 0x1000>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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ohci0: usb@30580000 {
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compatible = "generic-ohci";
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reg = <0x0 0x30580000 0x0 0x1000>;
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interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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spi: spi@33100000 {
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compatible = "arm,pl022","arm,primecell";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x33100000 0x0 0x100000>;
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clocks = <&spi_clk>, <&sup_clk>;
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clock-names = "spi_clk", "apb_pclk";
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num-cs = <4>;
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interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
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ctc,sysctrl = <&sysctrl>;
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status ="disabled";
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};
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qspi: qspi@10000000 {
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compatible = "ctc, igdaxi001a-qspi";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x10000000 0x0 0x10000>;
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pclk = <500000000>;
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num-cs = <2>;
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idle-cycle = <2>;
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post-cycle = <1>;
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pre-cycle = <2>;
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interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
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status = "disabled";
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};
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switch: switch@31100000 {
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compatible = "centec,dal-localbus";
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reg = <0x0 0x31100000 0x0 0x1000>,
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<0x0 0x33290000 0x0 0x10000>;
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interrupts = <GIC_SPI 128 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 129 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 130 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 131 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 132 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 133 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 134 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>,
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<GIC_SPI 135 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
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status ="disabled";
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};
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switch1: switch1@31101000 {
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compatible = "centec,switch";
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reg = <0x0 0x31101000 0x0 0x1000>;
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status ="disabled";
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};
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i2c0: i2c0@33700000{
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compatible = "ctc,i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x33700000 0x0 0x1000>;
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interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&i2c_clk>;
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status ="disabled";
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};
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i2c1: i2c1@33701000{
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compatible = "ctc,i2c";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x33701000 0x0 0x1000>;
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interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&i2c_clk>;
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status ="disabled";
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};
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pcie: pcie@20000000 {
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compatible = "centec,ctc5236-pcie";
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reg = <0x0 0x20000000 0x0 0x10000000
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0x0 0x30000000 0x0 0x1000>;
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reg-names = "cfg", "ctrl";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <1>;
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device_type = "pci";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
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<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi","aer","pme";
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msi-parent = <&pcie>;
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bus-range = <0 0xff>;
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ranges = <0x43000000 0 0x00000000 0 0x40000000 0 0x40000000>;
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num-lanes = <1>;
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ctc,sysctrl = <&sysctrl>;
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status ="disabled";
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};
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wtd0: wtd0@33500000{
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compatible = "arm,sp805-wdt", "arm,primecell";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x33500000 0x0 0x1000>;
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clocks = <&wdog_clk>, <&sup_clk>;
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clock-names = "wdog_clk", "apb_pclk";
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ctc,sysctrl = <&sysctrl>;
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interrupts = <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>;
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status="disabled";
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};
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wtd1: wtd1@33501000{
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compatible = "arm,sp805-wdt", "arm,primecell";
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#address-cells = <1>;
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#size-cells = <0>;
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reg = <0x0 0x33501000 0x0 0x1000>;
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clocks = <&wdog_clk>, <&sup_clk>;
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clock-names = "wdog_clk", "apb_pclk";
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ctc,sysctrl = <&sysctrl>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>;
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status="disabled";
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};
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sdhci: sdhci@30400000 {
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compatible = "centec,ctc5236-sdhci";
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status = "disabled";
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interrupt-parent = <&gic>;
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interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mmc_clk>;
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clock-names = "mmc_clk";
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ctc,sysctrl = <&sysctrl>;
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reg = <0x0 0x30400000 0x0 0x1000>;
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};
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timer0: timer0@33600000{
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compatible = "snps,dw-apb-timer";
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reg = <0x0 0x33600000 0x0 0x20>;
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clocks = <&timer_clk>;
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clock-names = "timer";
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interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
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DivNum = <0x3c>;
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status="disabled";
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};
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timer1: timer1@33600020{
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compatible = "snps,dw-apb-timer";
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reg = <0x0 0x33600020 0x0 0x20>;
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clocks = <&timer_clk>;
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clock-names = "timer";
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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DivNum = <0x3c>;
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status="disabled";
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};
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pwm: pwm@33200240{
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compatible = "centec-pwm";
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ctc,sysctrl = <&sysctrl>;
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#pwm-cells = <2>;
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status="disabled";
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};
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fan: fan-ctc5236 {
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compatible = "fan-ctc5236";
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pwms = <&pwm 0 1000000>,
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<&pwm 1 1000000>,
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<&pwm 2 1000000>,
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<&pwm 3 1000000>;
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pwm-names = "pwm1","pwm2","pwm3","pwm4";
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};
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gpio0: gpio@33610000 {
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compatible = "ctc,apb-gpio";
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reg = <0x0 0x33610000 0x0 0x10000>;
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#address-cells = <1>;
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#size-cells = <0>;
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porta: gpio-port@0 {
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compatible = "ctc,apb-gpio-porta";
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gpio-controller;
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#gpio-cells = <2>;
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ctc,nr-gpios = <16>;
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reg = <0>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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};
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portb: gpio-port@1 {
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compatible = "ctc,apb-gpio-portb";
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gpio-controller;
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#gpio-cells = <2>;
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ctc,nr-gpios = <18>;
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reg = <1>;
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
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};
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};
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pinctrl: pinctrl {
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compatible = "ctc,ctc5236-pinctrl";
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#address-cells = <0x2>;
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#size-cells = <0x2>;
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ctc,pinctrl-bank0 = <16>;
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ctc,pinctrl-bank1 = <8>;
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ctc,sysctrl = <&sysctrl>;
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status = "okay";
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};
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};
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};
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