188 lines
5.8 KiB
C
188 lines
5.8 KiB
C
/*
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* Unless you and Broadcom execute a separate written software license
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* agreement governing use of this software, this software is licensed to
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* you under the terms of the GNU General Public License version 2 (the
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* "GPL"), available at http://www.broadcom.com/licenses/GPLv2.php,
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* with the following added to such license:
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*
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* As a special exception, the copyright holders of this software give
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* you permission to link this software with independent modules, and to
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* copy and distribute the resulting executable under terms of your
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* choice, provided that you also meet, for each linked independent
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* module, the terms and conditions of the license of that module. An
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* independent module is a module which is not derived from this
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* software. The special exception does not apply to any modifications
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* of the software.
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*/
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/*
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* $Id: $
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* $Copyright: (c) 2015 Broadcom Corp.
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* All Rights Reserved.$
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*
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*/
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#include <shbde_mdio.h>
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/* iProc MDIO register offset */
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#define MII_MGMT_CTRL 0x0
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#define MII_MGMT_CMD_DATA 0x4
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/* iProc MII register with fields definition */
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#define MII_MGMT_CTRLr_MDCDIVf_SHFT 0
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#define MII_MGMT_CTRLr_MDCDIVf_MASK 0x7f
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#define MII_MGMT_CTRLr_BSYf_SHFT 8
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#define MII_MGMT_CTRLr_BSYf_MASK 0x1
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#define MII_MGMT_CMD_DATAr_DATAf_SHFT 0
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#define MII_MGMT_CMD_DATAr_DATAf_MASK 0xffff
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#define MII_MGMT_CMD_DATAr_TAf_SHFT 16
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#define MII_MGMT_CMD_DATAr_TAf_MASK 0x3
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#define MII_MGMT_CMD_DATAr_RAf_SHFT 18
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#define MII_MGMT_CMD_DATAr_RAf_MASK 0x1f
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#define MII_MGMT_CMD_DATAr_PAf_SHFT 23
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#define MII_MGMT_CMD_DATAr_PAf_MASK 0x1f
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#define MII_MGMT_CMD_DATAr_OPf_SHFT 28
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#define MII_MGMT_CMD_DATAr_OPf_MASK 0x3
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#define MII_MGMT_CMD_DATAr_SBf_SHFT 30
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#define MII_MGMT_CMD_DATAr_SBf_MASK 0x3
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/* Register field value set/get */
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#define REG_FIELD_SET(_r, _f, _r_val, _f_val) \
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_r_val = ((_r_val) & ~(_r##_##_f##_MASK << _r##_##_f##_SHFT)) | \
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(((_f_val) & _r##_##_f##_MASK) << _r##_##_f##_SHFT)
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#define REG_FIELD_GET(_r, _f, _r_val) \
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(((_r_val) >> _r##_##_f##_SHFT) & _r##_##_f##_MASK)
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#define LOG_OUT(_shbde, _lvl, _str, _prm) \
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if ((_shbde)->log_func) { \
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(_shbde)->log_func(_lvl, _str, _prm); \
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}
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#define LOG_ERR(_shbde, _str, _prm) LOG_OUT(_shbde, SHBDE_ERR, _str, _prm)
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#define LOG_WARN(_shbde, _str, _prm) LOG_OUT(_shbde, SHBDE_WARN, _str, _prm)
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#define LOG_DBG(_shbde, _str, _prm) LOG_OUT(_shbde, SHBDE_DBG, _str, _prm)
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static unsigned int
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mdio32_read(shbde_mdio_ctrl_t *smc, unsigned int offset)
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{
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if (!smc || !smc->io32_read) {
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return 0;
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}
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return smc->io32_read(smc->shbde, smc->regs, smc->base_addr + offset);
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}
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static void
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mdio32_write(shbde_mdio_ctrl_t *smc, unsigned int offset, unsigned int data)
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{
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if (!smc || !smc->io32_read) {
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return;
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}
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smc->io32_write(smc->shbde, smc->regs, smc->base_addr + offset, data);
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}
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static void
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wait_usec(shbde_mdio_ctrl_t *smc, int usec)
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{
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shbde_hal_t *shbde = smc->shbde;
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if (shbde && shbde->usleep) {
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shbde->usleep(usec);
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} else {
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int idx;
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volatile int count;
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for (idx = 0; idx < usec; idx++) {
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for (count = 0; count < 100; count++);
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}
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}
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}
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static int
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iproc_mdio_wait_for_busy(shbde_mdio_ctrl_t *smc)
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{
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int mii_busy;
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unsigned int reg_val;
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int count = 1000;
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/* Wait until MII is not busy */
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do {
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reg_val = mdio32_read(smc, MII_MGMT_CTRL);
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mii_busy = REG_FIELD_GET(MII_MGMT_CTRLr, BSYf, reg_val);
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if (!mii_busy) {
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break;
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}
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wait_usec(smc, 10);
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count --;
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} while (count > 0);
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return mii_busy;
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}
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int
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shbde_iproc_mdio_init(shbde_mdio_ctrl_t *smc)
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{
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shbde_hal_t *shbde = smc->shbde;
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unsigned int reg_val = 0;
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/* Enable the iProc internal MDIO interface */
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REG_FIELD_SET(MII_MGMT_CTRLr, MDCDIVf, reg_val, 0x7f);
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mdio32_write(smc, MII_MGMT_CTRL, reg_val);
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if (shbde && !shbde->usleep) {
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LOG_DBG(shbde, "shbde_mdio: no registration of usleep vector", 0);
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}
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wait_usec(smc, 100);
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return 0;
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}
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int
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shbde_iproc_mdio_read(shbde_mdio_ctrl_t *smc, unsigned int phy_addr,
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unsigned int reg, unsigned int *val)
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{
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unsigned int reg_val = 0;
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, SBf, reg_val, 0x1);
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, TAf, reg_val, 0x2);
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, OPf, reg_val, 0x2);
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, PAf, reg_val, phy_addr);
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, RAf, reg_val, reg);
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mdio32_write(smc, MII_MGMT_CMD_DATA, reg_val);
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if (iproc_mdio_wait_for_busy(smc)) {
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*val = 0;
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LOG_DBG(smc->shbde, "shbde_iproc_mdio_read busy", reg);
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return -1;
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}
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reg_val = mdio32_read(smc, MII_MGMT_CMD_DATA);
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*val = REG_FIELD_GET(MII_MGMT_CMD_DATAr, DATAf, reg_val);
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return 0;
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}
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int
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shbde_iproc_mdio_write(shbde_mdio_ctrl_t *smc, unsigned int phy_addr,
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unsigned int reg, unsigned int val)
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{
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unsigned int reg_val = 0;
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, SBf, reg_val, 0x1);
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, TAf, reg_val, 0x2);
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, OPf, reg_val, 0x1);
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, PAf, reg_val, phy_addr);
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, RAf, reg_val, reg);
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REG_FIELD_SET(MII_MGMT_CMD_DATAr, DATAf, reg_val, val);
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mdio32_write(smc, MII_MGMT_CMD_DATA, reg_val);
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if (iproc_mdio_wait_for_busy(smc)) {
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LOG_DBG(smc->shbde, "shbde_iproc_mdio_write busy", reg);
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return -1;
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}
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/* Wait for some time for the write to take effect */
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wait_usec(smc, 100);
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return 0;
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}
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