arista-nwolfe dfe7c1e720 [Arista]: Disable SA_EQUALS_DA trap on DNX LC SKUs (#17206) ... This change was submitted directly to 202205 but it's also needed in master and 202305 with SAI9.x #13346 There has been a couple CSPs for this as well: CS00012273013 - [7.1][J2, J2c+] Disable SA Equals DA trap on DNX CS00012320965 - SAI9.2: iBGP doesn't work due to SA_EQUALS_DA trap If SA_EQUALS_DA trap is enabled iBGP won't work as the Ethernet-IB0 ports are expected to get packets with SA==DA. In the VOQ chassis design, for outgoing control plane packets, the packets goes the recycle port for routing, therefore the dmac of the packet should be the asic router mac. The source mac is assigned by the kernel, so it is also the asic router mac.		2023-12-04 22:14:03 +00:00
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buffers_defaults_t2.j2	Update PG headroom settings ports based on port speed/cable length (#14908)	2023-05-19 08:19:27 -07:00
buffers.json.j2	Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards. (#11872)	2022-10-13 20:36:44 -07:00
context_config.json	Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards. (#11872)	2022-10-13 20:36:44 -07:00
j2p-a7800r3a-36d-36x400G.config.bcm	[Arista]: Disable SA_EQUALS_DA trap on DNX LC SKUs (#17206)	2023-12-04 22:14:03 +00:00
pg_profile_lookup.ini	Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards. (#11872)	2022-10-13 20:36:44 -07:00
port_config.ini	[devices/arista] Update asic_port_name in Arista LCs (#14234)	2023-04-06 10:53:42 -07:00
qos.json.j2	Updated default ECN settings for T2 chassis (#14388)	2023-05-04 10:01:09 -07:00
sai.profile	Add 36 port 400g SKU for x86_64-arista_7800r3a_36d series of Linecards. (#11872)	2022-10-13 20:36:44 -07:00