127 lines
3.7 KiB
Diff
127 lines
3.7 KiB
Diff
From 46563dcd511270f67a9e771497ccfc73907aa4d3 Mon Sep 17 00:00:00 2001
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From: Jiri Pirko <jiri@nvidia.com>
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Date: Thu, 25 Feb 2021 10:17:53 +0100
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Subject: [PATCH] mlxsw: reg: Add Management DownStream Device Tunneling
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Register
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The MDDT register allows deliver query and request messages
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(PRM registers, commands) to a DownStream device.
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Signed-off-by: Jiri Pirko <jiri@nvidia.com>
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---
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drivers/net/ethernet/mellanox/mlxsw/reg.h | 91 +++++++++++++++++++++++
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1 file changed, 91 insertions(+)
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diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
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index c1ce0b42e..f8c828e05 100644
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--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
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+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
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@@ -10482,6 +10482,96 @@ mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index,
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*p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload);
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}
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+/* MDDT - Management DownStream Device Tunneling Register
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+ * ------------------------------------------------------
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+ * This register allows deliver query and request messages (PRM registers,
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+ * commands) to a DownStream device.
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+ */
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+#define MLXSW_REG_MDDT_ID 0x9160
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+#define MLXSW_REG_MDDT_LEN 0x110
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+
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+MLXSW_REG_DEFINE(mddt, MLXSW_REG_MDDT_ID, MLXSW_REG_MDDT_LEN);
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+
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+/* reg_mddt_slot_index
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+ * Slot index.
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+ * Access: Index
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+ */
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+
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+MLXSW_ITEM32(reg, mddt, slot_index, 0x00, 8, 4);
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+
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+/* reg_mddt_device_index
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+ * Device index.
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+ * Access: Index
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+ */
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+MLXSW_ITEM32(reg, mddt, device_index, 0x00, 0, 8);
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+
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+/* reg_mddt_read_size
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+ * Read size in D-Words.
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+ * Access: OP
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+ */
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+MLXSW_ITEM32(reg, mddt, read_size, 0x04, 24, 8);
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+
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+/* reg_mddt_write_size
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+ * Write size in D-Words.
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+ * Access: OP
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+ */
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+MLXSW_ITEM32(reg, mddt, write_size, 0x04, 16, 8);
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+
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+enum mlxsw_reg_mddt_status {
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+ MLXSW_REG_MDDT_STATUS_OK,
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+};
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+
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+/* reg_mddt_status
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+ * Return code of the Downstream Device to the register that was sent.
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+ * Access: RO
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+ */
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+MLXSW_ITEM32(reg, mddt, status, 0x0C, 24, 8);
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+
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+enum mlxsw_reg_mddt_method {
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+ MLXSW_REG_MDDT_METHOD_QUERY,
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+ MLXSW_REG_MDDT_METHOD_WRITE,
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+};
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+
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+/* reg_mddt_method
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+ * Access: OP
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+ */
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+MLXSW_ITEM32(reg, mddt, method, 0x0C, 22, 2);
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+
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+/* reg_mddt_register_id
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+ * Access: Index
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+ */
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+MLXSW_ITEM32(reg, mddt, register_id, 0x0C, 0, 16);
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+
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+#define MLXSW_REG_MDDT_PAYLOAD_OFFSET 0x0C
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+#define MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN 4
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+
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+static inline char *mlxsw_reg_mddt_inner_payload(char *payload)
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+{
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+ return payload + MLXSW_REG_MDDT_PAYLOAD_OFFSET +
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+ MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN;
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+}
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+
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+static inline void mlxsw_reg_mddt_pack(char *payload, u8 slot_index,
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+ u8 device_index,
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+ enum mlxsw_reg_mddt_method method,
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+ const struct mlxsw_reg_info *reg,
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+ char **inner_payload)
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+{
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+ int len = reg->len + MLXSW_REG_MDDT_PRM_REGISTER_HEADER_LEN;
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+
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+ if (WARN_ON(len + MLXSW_REG_MDDT_PAYLOAD_OFFSET > MLXSW_REG_MDDT_LEN))
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+ len = MLXSW_REG_MDDT_LEN - MLXSW_REG_MDDT_PAYLOAD_OFFSET;
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+
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+ MLXSW_REG_ZERO(mddt, payload);
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+ mlxsw_reg_mddt_slot_index_set(payload, slot_index);
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+ mlxsw_reg_mddt_device_index_set(payload, device_index);
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+ mlxsw_reg_mddt_method_set(payload, method);
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+ mlxsw_reg_mddt_register_id_set(payload, reg->id);
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+ mlxsw_reg_mddt_read_size_set(payload, len / 4);
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+ mlxsw_reg_mddt_write_size_set(payload, len / 4);
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+ *inner_payload = mlxsw_reg_mddt_inner_payload(payload);
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+}
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+
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/* MDDQ - Management DownStream Device Query Register
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* --------------------------------------------------
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* This register allows to query the DownStream device properties. The desired
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@@ -11952,6 +12042,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(mgpir),
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MLXSW_REG(mtecr),
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MLXSW_REG(mbct),
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+ MLXSW_REG(mddt),
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MLXSW_REG(mddq),
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MLXSW_REG(mddc),
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MLXSW_REG(mfde),
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--
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2.30.2
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