155 lines
4.6 KiB
Diff
155 lines
4.6 KiB
Diff
From 618665ccbf600c2838fb2e181246aef0fa90bac2 Mon Sep 17 00:00:00 2001
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From: Jiri Pirko <jiri@nvidia.com>
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Date: Thu, 10 Dec 2020 18:27:38 +0100
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Subject: [PATCH] mlxsw: reg: Add Management Binary Code Transfer Register
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The MBCT register allows to transfer binary codes from the Host to
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the management FW by transferring it by chunks of maximum 1KB.
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Signed-off-by: Jiri Pirko <jiri@nvidia.com>
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---
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drivers/net/ethernet/mellanox/mlxsw/reg.h | 120 ++++++++++++++++++++++
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1 file changed, 120 insertions(+)
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diff --git a/drivers/net/ethernet/mellanox/mlxsw/reg.h b/drivers/net/ethernet/mellanox/mlxsw/reg.h
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index 9cbdf407f..89b21910f 100644
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--- a/drivers/net/ethernet/mellanox/mlxsw/reg.h
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+++ b/drivers/net/ethernet/mellanox/mlxsw/reg.h
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@@ -10297,6 +10297,125 @@ mlxsw_reg_mgpir_unpack(char *payload, u8 *num_of_devices,
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*num_of_slots = mlxsw_reg_mgpir_num_of_slots_get(payload);
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}
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+/* MBCT - Management Binary Code Transfer Register
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+ * -----------------------------------------------
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+ * This register allows to transfer binary codes from the Host to
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+ * the management FW by transferring it by chunks of maximum 1KB.
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+ */
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+#define MLXSW_REG_MBCT_ID 0x9120
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+#define MLXSW_REG_MBCT_LEN 0x420
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+
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+MLXSW_REG_DEFINE(mbct, MLXSW_REG_MBCT_ID, MLXSW_REG_MBCT_LEN);
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+
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+/* reg_mbct_slot_index
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+ * Slot index. 0 is reserved.
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+ * Access: Index
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+ */
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+MLXSW_ITEM32(reg, mbct, slot_index, 0x00, 0, 4);
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+
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+/* reg_mbct_data_size
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+ * Actual data field size in bytes for the current data transfer.
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+ * Access: WO
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+ */
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+MLXSW_ITEM32(reg, mbct, data_size, 0x04, 0, 11);
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+
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+enum mlxsw_reg_mbct_op {
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+ MLXSW_REG_MBCT_OP_ERASE_INI_IMAGE = 1,
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+ MLXSW_REG_MBCT_OP_DATA_TRANSFER, /* Download */
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+ MLXSW_REG_MBCT_OP_ACTIVATE,
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+ MLXSW_REG_MBCT_OP_CLEAR_ERRORS = 6,
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+ MLXSW_REG_MBCT_OP_QUERY_STATUS,
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+};
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+
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+/* reg_mbct_op
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+ * Access: OP
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+ */
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+MLXSW_ITEM32(reg, mbct, op, 0x08, 28, 4);
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+
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+/* reg_mbct_last
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+ * Indicates that the current data field is the last chunk of the INI.
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+ * Access: WO
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+ */
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+MLXSW_ITEM32(reg, mbct, last, 0x08, 26, 1);
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+
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+/* reg_mbct_oee
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+ * Opcode Event Enable. When set an event will be sent once the opcode
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+ * was executed and the fsm_state has changed.
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+ * Access: WO
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+ */
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+MLXSW_ITEM32(reg, mbct, oee, 0x08, 25, 1);
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+
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+enum mlxsw_reg_mbct_status {
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+ /* Partial data transfer completed successfully and ready for next
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+ * data transfer.
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+ */
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+ MLXSW_REG_MBCT_STATUS_PART_DATA = 2,
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+ MLXSW_REG_MBCT_STATUS_LAST_DATA,
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+ MLXSW_REG_MBCT_STATUS_ERASE_COMPLETE,
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+ /* Error - trying to erase INI while it being used. */
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+ MLXSW_REG_MBCT_STATUS_ERROR_INI_IN_USE,
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+ /* Last data transfer completed, applying magic pattern. */
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+ MLXSW_REG_MBCT_STATUS_ERASE_FAILED = 7,
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+ MLXSW_REG_MBCT_STATUS_INI_ERROR,
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+ MLXSW_REG_MBCT_STATUS_ACTIVATION_FAILED,
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+ MLXSW_REG_MBCT_STATUS_ILLEGAL_OPERATION = 11,
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+};
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+
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+/* reg_mbct_status
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+ * Status.
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+ * Access: RO
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+ */
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+MLXSW_ITEM32(reg, mbct, status, 0x0C, 24, 5);
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+
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+enum mlxsw_reg_mbct_fsm_state {
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+ MLXSW_REG_MBCT_FSM_STATE_INI_IN_USE = 5,
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+ MLXSW_REG_MBCT_FSM_STATE_ERROR = 6,
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+};
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+
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+/* reg_mbct_fsm_state
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+ * FSM state.
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+ * Access: RO
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+ */
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+MLXSW_ITEM32(reg, mbct, fsm_state, 0x0C, 16, 4);
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+
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+#define MLXSW_REG_MBCT_DATA_LEN 1024
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+
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+/* reg_mbct_data
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+ * Up to 1KB of data.
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+ * Access: WO
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+ */
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+MLXSW_ITEM_BUF(reg, mbct, data, 0x20, MLXSW_REG_MBCT_DATA_LEN);
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+
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+static inline void mlxsw_reg_mbct_pack(char *payload, u8 slot_index,
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+ enum mlxsw_reg_mbct_op op,
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+ u16 data_size, bool last, bool oee,
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+ const char *data)
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+{
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+ MLXSW_REG_ZERO(mbct, payload);
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+ mlxsw_reg_mbct_slot_index_set(payload, slot_index);
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+ mlxsw_reg_mbct_op_set(payload, op);
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+ mlxsw_reg_mbct_oee_set(payload, oee);
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+ if (op == MLXSW_REG_MBCT_OP_DATA_TRANSFER) {
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+ if (WARN_ON(data_size > MLXSW_REG_MBCT_DATA_LEN))
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+ return;
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+ mlxsw_reg_mbct_data_size_set(payload, data_size);
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+ mlxsw_reg_mbct_last_set(payload, last);
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+ mlxsw_reg_mbct_data_memcpy_to(payload, data);
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+ }
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+}
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+
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+static inline void
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+mlxsw_reg_mbct_unpack(const char *payload, u8 *p_slot_index,
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+ enum mlxsw_reg_mbct_status *p_status,
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+ enum mlxsw_reg_mbct_fsm_state *p_fsm_state)
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+{
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+ if (p_slot_index)
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+ *p_slot_index = mlxsw_reg_mbct_slot_index_get(payload);
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+ *p_status = mlxsw_reg_mbct_status_get(payload);
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+ if (p_fsm_state)
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+ *p_fsm_state = mlxsw_reg_mbct_fsm_state_get(payload);
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+}
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+
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/* MDDQ - Management DownStream Device Query Register
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* --------------------------------------------------
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* This register allows to query the DownStream device properties. The desired
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@@ -11765,6 +11884,7 @@ static const struct mlxsw_reg_info *mlxsw_reg_infos[] = {
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MLXSW_REG(mtptpt),
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MLXSW_REG(mfgd),
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MLXSW_REG(mgpir),
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+ MLXSW_REG(mbct),
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MLXSW_REG(mddq),
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MLXSW_REG(mddc),
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MLXSW_REG(mfde),
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--
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2.30.2
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