562 lines
16 KiB
C
562 lines
16 KiB
C
/*
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* dx010_cpld.c - driver for SeaStone's CPLD
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*
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* Copyright (C) 2017 Celestica Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/interrupt.h>
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#include <linux/module.h>
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#include <linux/pci.h>
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#include <linux/kernel.h>
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#include <linux/stddef.h>
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#include <linux/delay.h>
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#include <linux/ioport.h>
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#include <linux/init.h>
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#include <linux/i2c.h>
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#include <linux/acpi.h>
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#include <linux/io.h>
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#include <linux/dmi.h>
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#include <linux/slab.h>
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#include <linux/wait.h>
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#include <linux/err.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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#include <uapi/linux/stat.h>
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#define DRIVER_NAME "dx010_cpld"
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#define RESET0108 0x250
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#define RESET0910 0x251
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#define RESET1118 0x2d0
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#define RESET1921 0x2d1
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#define RESET2229 0x3d0
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#define RESET3032 0x3d1
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#define LPMOD0108 0x252
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#define LPMOD0910 0x253
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#define LPMOD1118 0x2d2
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#define LPMOD1921 0x2d3
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#define LPMOD2229 0x3d2
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#define LPMOD3032 0x3d3
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#define ABS0108 0x254
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#define ABS0910 0x255
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#define ABS1118 0x2d4
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#define ABS1921 0x2d5
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#define ABS2229 0x3d4
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#define ABS3032 0x3d5
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#define INT0108 0x256
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#define INT0910 0x257
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#define INT1118 0x2d6
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#define INT1921 0x2d7
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#define INT2229 0x3d6
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#define INT3032 0x3d7
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#define LENGTH_PORT_CPLD 34
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#define PORT_BANK1_START 1
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#define PORT_BANK1_END 10
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#define PORT_BANK2_START 11
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#define PORT_BANK2_END 21
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#define PORT_BANK3_START 22
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#define PORT_BANK3_END 32
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#define PORT_SFPP1 33
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#define PORT_SFPP2 34
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#define PORT_ID_BANK1 0x210
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#define PORT_ID_BANK2 0x290
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#define PORT_ID_BANK3 0x390
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#define OPCODE_ID_BANK1 0x211
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#define OPCODE_ID_BANK2 0x291
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#define OPCODE_ID_BANK3 0x391
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#define DEVADDR_ID_BANK1 0x212
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#define DEVADDR_ID_BANK2 0x292
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#define DEVADDR_ID_BANK3 0x392
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#define CMDBYT_ID_BANK1 0x213
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#define CMDBYT_ID_BANK2 0x293
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#define CMDBYT_ID_BANK3 0x393
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#define WRITE_ID_BANK1 0x220
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#define WRITE_ID_BANK2 0x2A0
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#define WRITE_ID_BANK3 0x3A0
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#define READ_ID_BANK1 0x230
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#define READ_ID_BANK2 0x2B0
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#define READ_ID_BANK3 0x3B0
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#define SSRR_ID_BANK1 0x216
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#define SSRR_ID_BANK2 0x296
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#define SSRR_ID_BANK3 0x396
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#define HST_CNTL2_QUICK 0x00
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#define HST_CNTL2_BYTE 0x01
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#define HST_CNTL2_BYTE_DATA 0x02
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#define HST_CNTL2_WORD_DATA 0x03
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#define HST_CNTL2_BLOCK 0x05
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struct dx010_i2c_data {
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int portid;
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};
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struct dx010_cpld_data {
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struct i2c_adapter *i2c_adapter[LENGTH_PORT_CPLD];
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struct mutex cpld_lock;
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};
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struct dx010_cpld_data *cpld_data;
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static ssize_t get_reset(struct device *dev, struct device_attribute *devattr,
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char *buf)
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{
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unsigned long reset = 0;
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mutex_lock(&cpld_data->cpld_lock);
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reset =
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(inb(RESET3032) & 0x07) << (24+5) |
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inb(RESET2229) << (24-3) |
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(inb(RESET1921) & 0x07) << (16 + 2) |
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inb(RESET1118) << (16-6) |
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(inb(RESET0910) & 0x03 ) << 8 |
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inb(RESET0108);
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mutex_unlock(&cpld_data->cpld_lock);
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return sprintf(buf,"0x%8.8lx\n", reset & 0xffffffff);
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}
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static ssize_t set_reset(struct device *dev, struct device_attribute *devattr,
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const char *buf, size_t count)
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{
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unsigned long reset;
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int err;
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mutex_lock(&cpld_data->cpld_lock);
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err = kstrtoul(buf, 16, &reset);
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if (err)
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{
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mutex_unlock(&cpld_data->cpld_lock);
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return err;
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}
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outb( (reset >> 0) & 0xFF, RESET0108);
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outb( (reset >> 8) & 0x03, RESET0910);
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outb( (reset >> 10) & 0xFF, RESET1118);
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outb( (reset >> 18) & 0x07, RESET1921);
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outb( (reset >> 21) & 0xFF, RESET2229);
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outb( (reset >> 29) & 0x07, RESET3032);
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mutex_unlock(&cpld_data->cpld_lock);
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return count;
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}
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static ssize_t get_lpmode(struct device *dev, struct device_attribute *devattr,
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char *buf)
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{
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unsigned long lpmod = 0;
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mutex_lock(&cpld_data->cpld_lock);
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lpmod =
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(inb(LPMOD3032) & 0x07) << (24+5) |
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inb(LPMOD2229) << (24-3) |
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(inb(LPMOD1921) & 0x07) << (16 + 2) |
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inb(LPMOD1118) << (16-6) |
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(inb(LPMOD0910) & 0x03 ) << 8 |
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inb(LPMOD0108);
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mutex_unlock(&cpld_data->cpld_lock);
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return sprintf(buf,"0x%8.8lx\n", lpmod & 0xffffffff);
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}
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static ssize_t set_lpmode(struct device *dev, struct device_attribute *devattr,
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const char *buf, size_t count)
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{
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unsigned long lpmod;
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int err;
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mutex_lock(&cpld_data->cpld_lock);
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err = kstrtoul(buf, 16, &lpmod);
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if (err)
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{
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mutex_unlock(&cpld_data->cpld_lock);
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return err;
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}
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outb( (lpmod >> 0) & 0xFF, LPMOD0108);
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outb( (lpmod >> 8) & 0x03, LPMOD0910);
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outb( (lpmod >> 10) & 0xFF, LPMOD1118);
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outb( (lpmod >> 18) & 0x07, LPMOD1921);
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outb( (lpmod >> 21) & 0xFF, LPMOD2229);
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outb( (lpmod >> 29) & 0x07, LPMOD3032);
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mutex_unlock(&cpld_data->cpld_lock);
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return count;
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}
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static ssize_t get_modprs(struct device *dev, struct device_attribute *devattr,
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char *buf)
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{
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unsigned long present;
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mutex_lock(&cpld_data->cpld_lock);
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present =
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(inb(ABS3032) & 0x07) << (24+5) |
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inb(ABS2229) << (24-3) |
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(inb(ABS1921) & 0x07) << (16 + 2) |
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inb(ABS1118) << (16-6) |
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(inb(ABS0910) & 0x03) << 8 |
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inb(ABS0108);
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mutex_unlock(&cpld_data->cpld_lock);
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return sprintf(buf,"0x%8.8lx\n", present & 0xffffffff);
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}
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static ssize_t get_modirq(struct device *dev, struct device_attribute *devattr,
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char *buf)
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{
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unsigned long irq;
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mutex_lock(&cpld_data->cpld_lock);
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irq =
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(inb(INT3032) & 0x07) << (24+5) |
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inb(INT2229) << (24-3) |
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(inb(INT1921) & 0x07) << (16 + 2) |
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inb(INT1118) << (16-6) |
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(inb(INT0910) & 0x03) << 8 |
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inb(INT0108);
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mutex_unlock(&cpld_data->cpld_lock);
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return sprintf(buf,"0x%8.8lx\n", irq & 0xffffffff);
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}
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static DEVICE_ATTR(qsfp_reset, S_IRUGO | S_IWUSR, get_reset, set_reset);
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static DEVICE_ATTR(qsfp_lpmode, S_IRUGO | S_IWUSR, get_lpmode, set_lpmode);
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static DEVICE_ATTR(qsfp_modprs, S_IRUGO, get_modprs, NULL);
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static DEVICE_ATTR(qsfp_modirq, S_IRUGO, get_modirq, NULL);
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static struct attribute *dx010_lpc_attrs[] = {
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&dev_attr_qsfp_reset.attr,
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&dev_attr_qsfp_lpmode.attr,
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&dev_attr_qsfp_modprs.attr,
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&dev_attr_qsfp_modirq.attr,
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NULL,
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};
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static struct attribute_group dx010_lpc_attr_grp = {
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.attrs = dx010_lpc_attrs,
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};
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static struct resource cel_dx010_lpc_resources[] = {
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{
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.flags = IORESOURCE_IO,
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},
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};
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static void cel_dx010_lpc_dev_release( struct device * dev)
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{
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return;
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}
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static struct platform_device cel_dx010_lpc_dev = {
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.name = DRIVER_NAME,
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.id = -1,
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.num_resources = ARRAY_SIZE(cel_dx010_lpc_resources),
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.resource = cel_dx010_lpc_resources,
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.dev = {
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.release = cel_dx010_lpc_dev_release,
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}
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};
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/**
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* Read eeprom of QSFP device.
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* @param a i2c adapter.
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* @param addr address to read.
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* @param new_data QSFP port number struct.
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* @param cmd i2c command.
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* @return 0 if not error, else the error code.
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*/
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static int i2c_read_eeprom(struct i2c_adapter *a, u16 addr,
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struct dx010_i2c_data *new_data, u8 cmd, union i2c_smbus_data *data){
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u32 reg;
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int ioBase=0;
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char byte;
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short temp;
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short portid, opcode, devaddr, cmdbyte0, ssrr, writedata, readdata;
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__u16 word_data;
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int error = -EIO;
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mutex_lock(&cpld_data->cpld_lock);
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if (((new_data->portid >= PORT_BANK1_START)
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&& (new_data->portid <= PORT_BANK1_END))
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|| (new_data->portid == PORT_SFPP1)
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|| (new_data->portid == PORT_SFPP2))
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{
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portid = PORT_ID_BANK1;
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opcode = OPCODE_ID_BANK1;
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devaddr = DEVADDR_ID_BANK1;
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cmdbyte0 = CMDBYT_ID_BANK1;
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ssrr = SSRR_ID_BANK1;
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writedata = WRITE_ID_BANK1;
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readdata = READ_ID_BANK1;
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}else if ((new_data->portid >= PORT_BANK2_START) && (new_data->portid <= PORT_BANK2_END)){
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portid = PORT_ID_BANK2;
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opcode = OPCODE_ID_BANK2;
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devaddr = DEVADDR_ID_BANK2;
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cmdbyte0 = CMDBYT_ID_BANK2;
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ssrr = SSRR_ID_BANK2;
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writedata = WRITE_ID_BANK2;
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readdata = READ_ID_BANK2;
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}else if ((new_data->portid >= PORT_BANK3_START) && (new_data->portid <= PORT_BANK3_END)){
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portid = PORT_ID_BANK3;
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opcode = OPCODE_ID_BANK3;
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devaddr = DEVADDR_ID_BANK3;
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cmdbyte0 = CMDBYT_ID_BANK3;
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ssrr = SSRR_ID_BANK3;
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writedata = WRITE_ID_BANK3;
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readdata = READ_ID_BANK3;
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}else{
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/* Invalid parameter! */
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error = -EINVAL;
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goto exit;
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}
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while ((inb(ioBase + ssrr) & 0x40));
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if ((inb(ioBase + ssrr) & 0x80) == 0x80) {
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error = -EIO;
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/* Read error reset the port */
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outb(0x00, ioBase + ssrr);
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udelay(3000);
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outb(0x01, ioBase + ssrr);
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goto exit;
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}
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byte = 0x40 +new_data->portid;
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reg = cmd;
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outb(byte, ioBase + portid);
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outb(reg,ioBase + cmdbyte0);
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byte = 33;
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outb(byte, ioBase + opcode);
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addr = addr << 1;
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addr |= 0x01;
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outb(addr, ioBase + devaddr);
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while ((inb(ioBase + ssrr) & 0x40))
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{
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udelay(100);
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}
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if ((inb(ioBase + ssrr) & 0x80) == 0x80) {
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/* Read error reset the port */
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error = -EIO;
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outb(0x00, ioBase + ssrr);
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udelay(3000);
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outb(0x01, ioBase + ssrr);
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goto exit;
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}
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temp = ioBase + readdata;
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word_data = inb(temp);
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word_data |= (inb(++temp) << 8);
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mutex_unlock(&cpld_data->cpld_lock);
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data->word = word_data;
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return 0;
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exit:
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mutex_unlock(&cpld_data->cpld_lock);
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return error;
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}
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static int dx010_i2c_access(struct i2c_adapter *a, u16 addr,
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unsigned short flags, char rw, u8 cmd,
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int size, union i2c_smbus_data *data)
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{
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int error = 0;
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struct dx010_i2c_data *new_data;
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/* Write the command register */
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new_data = i2c_get_adapdata(a);
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/* Map the size to what the chip understands */
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switch (size) {
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case I2C_SMBUS_QUICK:
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size = HST_CNTL2_QUICK;
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break;
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case I2C_SMBUS_BYTE:
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size = HST_CNTL2_BYTE;
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break;
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case I2C_SMBUS_BYTE_DATA:
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size = HST_CNTL2_BYTE_DATA;
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break;
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case I2C_SMBUS_WORD_DATA:
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size = HST_CNTL2_WORD_DATA;
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break;
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case I2C_SMBUS_BLOCK_DATA:
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size = HST_CNTL2_BLOCK;
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break;
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default:
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dev_warn(&a->dev, "Unsupported transaction %d\n", size);
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error = -EOPNOTSUPP;
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goto Done;
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}
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switch (size) {
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case HST_CNTL2_BYTE: /* Result put in SMBHSTDAT0 */
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break;
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case HST_CNTL2_BYTE_DATA:
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break;
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case HST_CNTL2_WORD_DATA:
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if( 0 == i2c_read_eeprom(a,addr,new_data,cmd,data)){
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error = 0;
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}else{
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error = -EIO;
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}
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break;
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}
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Done:
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return error;
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}
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static u32 dx010_i2c_func(struct i2c_adapter *a)
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{
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return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
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I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
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I2C_FUNC_SMBUS_BLOCK_DATA;
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}
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static const struct i2c_algorithm dx010_i2c_algorithm = {
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.smbus_xfer = dx010_i2c_access,
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.functionality = dx010_i2c_func,
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};
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static struct i2c_adapter * cel_dx010_i2c_init(struct platform_device *pdev, int portid)
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{
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int error;
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struct i2c_adapter *new_adapter;
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struct dx010_i2c_data *new_data;
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new_adapter = kzalloc(sizeof(*new_adapter), GFP_KERNEL);
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if (!new_adapter)
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return NULL;
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new_adapter->dev.parent = &pdev->dev;
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new_adapter->owner = THIS_MODULE;
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new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
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new_adapter->algo = &dx010_i2c_algorithm;
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snprintf(new_adapter->name, sizeof(new_adapter->name),
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"SMBus dx010 i2c Adapter portid@%04x", portid);
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new_data = kzalloc(sizeof(*new_data), GFP_KERNEL);
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if (!new_data)
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return NULL;
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new_data->portid = portid;
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i2c_set_adapdata(new_adapter,new_data);
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error = i2c_add_adapter(new_adapter);
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if(error)
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return NULL;
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return new_adapter;
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};
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static int cel_dx010_lpc_drv_probe(struct platform_device *pdev)
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{
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struct resource *res;
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int ret =0;
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int portid_count;
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cpld_data = devm_kzalloc(&pdev->dev, sizeof(struct dx010_cpld_data),
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GFP_KERNEL);
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if (!cpld_data)
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return -ENOMEM;
|
|
|
|
mutex_init(&cpld_data->cpld_lock);
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_IO, 0);
|
|
if (unlikely(!res)) {
|
|
printk(KERN_ERR " Specified Resource Not Available...\n");
|
|
return -1;
|
|
}
|
|
|
|
ret = sysfs_create_group(&pdev->dev.kobj, &dx010_lpc_attr_grp);
|
|
if (ret) {
|
|
printk(KERN_ERR "Cannot create sysfs\n");
|
|
}
|
|
|
|
for(portid_count=1 ; portid_count<=LENGTH_PORT_CPLD ; portid_count++)
|
|
cpld_data->i2c_adapter[portid_count-1] =
|
|
cel_dx010_i2c_init(pdev, portid_count);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int cel_dx010_lpc_drv_remove(struct platform_device *pdev)
|
|
{
|
|
int portid_count;
|
|
|
|
sysfs_remove_group(&pdev->dev.kobj, &dx010_lpc_attr_grp);
|
|
|
|
for (portid_count=1 ; portid_count<=LENGTH_PORT_CPLD ; portid_count++)
|
|
i2c_del_adapter(cpld_data->i2c_adapter[portid_count-1]);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver cel_dx010_lpc_drv = {
|
|
.probe = cel_dx010_lpc_drv_probe,
|
|
.remove = __exit_p(cel_dx010_lpc_drv_remove),
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
},
|
|
};
|
|
|
|
int cel_dx010_lpc_init(void)
|
|
{
|
|
platform_device_register(&cel_dx010_lpc_dev);
|
|
platform_driver_register(&cel_dx010_lpc_drv);
|
|
|
|
return 0;
|
|
}
|
|
|
|
void cel_dx010_lpc_exit(void)
|
|
{
|
|
platform_driver_unregister(&cel_dx010_lpc_drv);
|
|
platform_device_unregister(&cel_dx010_lpc_dev);
|
|
}
|
|
|
|
module_init(cel_dx010_lpc_init);
|
|
module_exit(cel_dx010_lpc_exit);
|
|
|
|
MODULE_AUTHOR("Abhisit Sangjan <asang@celestica.com>");
|
|
MODULE_AUTHOR("Pariwat Leamsumran <pleamsum@celestica.com>");
|
|
MODULE_DESCRIPTION("Celestica SeaStone DX010 LPC Driver");
|
|
MODULE_LICENSE("GPL");
|