0704ff5e6c
Why I did it Some of the platform vendors use FPGA in the HW design. This FPGA is connected to the CPU via PCIe interface. This FPGA also works as an I2C controller having other devices attached to the I2C channels emanating from it. Adding a common module, a driver and a platform specific algorithm module to be used for such FPGA in PDDF. How I did it Added 'pddf_fpgapci_module', 'pddf_fpgapci_driver' and a sample algorithm module for Xilinx device 7021. Kernel modules which takes the platform dependent data from PDDF JSON files and initialises the PCIe FPGA. The sample algorithm module can be used by the ODMs in case the communication algorithms are same for their device. Else, they need to come up with similar algo module. How to verify it Any platform having such an FPGA and brought up using PDDF would use these kernel modules. The detail representation of such a device in PDDF JSON file is covered in the HLD.
37 lines
723 B
C
37 lines
723 B
C
/*
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*
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* Description:
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* This is the required header file for customed i2c algorithms
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*/
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#ifndef __PDDF_I2C_ALGO_H__
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#define __PDDF_I2C_ALGO_H__
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#include "pddf_client_defs.h"
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/* max number of adapters */
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#define I2C_PCI_MAX_BUS 16
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/**
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* struct fpgapci_devdata - PCI device data structure
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* support one device per PCIe
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*/
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struct fpgapci_devdata {
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struct pci_dev *pci_dev;
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/* kernels virtual addr for fpga_data_base_addr */
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void * __iomem fpga_data_base_addr;
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/* kernels virtual addr. for the i2c_ch_base_addr */
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void * __iomem fpga_i2c_ch_base_addr;
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/* size per i2c_ch */
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int fpga_i2c_ch_size;
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/* number of supported virtual i2c buses */
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int max_fpga_i2c_ch;
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size_t bar_length;
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};
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#endif
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