Stephen Sun c8277a4eba Update buffer configuration for SKUs based on SN3800 (#5320) ... C64: 32 100G down links and 32 100G up links. D112C8: 112 50G down links and 8 100G up links. D24C52: 24 50G down links, 20 100G down links, and 32 100G up links. D28C50: 28 50G down links, 18 100G down links, and 32 100G up links. Signed-off-by: Stephen Sun <stephens@nvidia.com>		2020-09-22 19:10:18 +03:00
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buffers_defaults_t0.j2	Update buffer configuration for SKUs based on SN3800 (#5320)	2020-09-22 19:10:18 +03:00
buffers_defaults_t1.j2	Update buffer configuration for SKUs based on SN3800 (#5320)	2020-09-22 19:10:18 +03:00
buffers.json.j2	[mellanox]: Add new Mellanox-SN3800-D112C8 sku. (#4085)	2020-01-30 18:54:09 -08:00
pg_profile_lookup.ini	Support single ingress pool for MSFT SKUs and optimize headroom calculation (#4686)	2020-08-13 13:12:09 +03:00
port_config.ini	[Mellanox] Change port index in port_config.ini to 1-based (#4781)	2020-06-23 17:21:36 -07:00
qos.json.j2	[mellanox]: Add new Mellanox-SN3800-D112C8 sku. (#4085)	2020-01-30 18:54:09 -08:00
sai_3800_112x50g_8x100g.xml	[Mellanox]Mellanox-SN3800-D112C8 support warm-reboot (#4482)	2020-04-27 12:47:44 -07:00
sai.profile	[devices][Mellanox] create sai.xml for MSN3800-D112-C8 (#4334)	2020-03-31 11:25:52 -07:00