f01076ea2a
Why I did it Added Support for Dell EMC S5212f platform How I did it Implemented the support for Dell EMC S5212f platform Platform: x86_64-dellemc_s5212f_c3538-r0 HwSKU: DellEMC-S5212f-P-25G ASIC: broadcom ASIC Count: 1 How to verify it Verified the show command outputs
160 lines
4.7 KiB
Plaintext
160 lines
4.7 KiB
Plaintext
portmap_1.0=29:25
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portmap_2.0=30:25
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portmap_3.0=31:25
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portmap_4.0=32:25
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portmap_5.0=33:25
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portmap_6.0=34:25
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portmap_7.0=35:25
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portmap_8.0=36:25
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portmap_9.0=37:25
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portmap_10.0=38:25
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portmap_11.0=39:25
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portmap_12.0=40:25
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portmap_33.0=41:100
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portmap_37.0=45:100
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portmap_41.0=49:100
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phy_chain_tx_lane_map_physical{29.0}=0x0123
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phy_chain_rx_lane_map_physical{29.0}=0x1032
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phy_chain_tx_lane_map_physical{33.0}=0x0123
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phy_chain_rx_lane_map_physical{33.0}=0x1032
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phy_chain_tx_lane_map_physical{37.0}=0x2013
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phy_chain_rx_lane_map_physical{37.0}=0x0231
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phy_chain_tx_lane_map_physical{41.0}=0x2301
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phy_chain_rx_lane_map_physical{41.0}=0x1230
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phy_chain_tx_lane_map_physical{45.0}=0x3120
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phy_chain_rx_lane_map_physical{45.0}=0x0213
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phy_chain_tx_lane_map_physical{49.0}=0x2301
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phy_chain_rx_lane_map_physical{49.0}=0x1032
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phy_chain_tx_polarity_flip_physical{29.0}=0x1
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phy_chain_rx_polarity_flip_physical{29.0}=0x1
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phy_chain_tx_polarity_flip_physical{30.0}=0x1
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phy_chain_rx_polarity_flip_physical{30.0}=0x1
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phy_chain_tx_polarity_flip_physical{31.0}=0x1
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phy_chain_rx_polarity_flip_physical{31.0}=0x1
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phy_chain_tx_polarity_flip_physical{32.0}=0x1
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phy_chain_rx_polarity_flip_physical{32.0}=0x1
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phy_chain_tx_polarity_flip_physical{33.0}=0x1
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phy_chain_rx_polarity_flip_physical{33.0}=0x1
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phy_chain_tx_polarity_flip_physical{34.0}=0x1
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phy_chain_rx_polarity_flip_physical{34.0}=0x1
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phy_chain_tx_polarity_flip_physical{35.0}=0x1
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phy_chain_rx_polarity_flip_physical{35.0}=0x1
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phy_chain_tx_polarity_flip_physical{36.0}=0x1
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phy_chain_rx_polarity_flip_physical{36.0}=0x1
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phy_chain_tx_polarity_flip_physical{37.0}=0x0
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phy_chain_rx_polarity_flip_physical{37.0}=0x0
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phy_chain_tx_polarity_flip_physical{38.0}=0x1
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phy_chain_rx_polarity_flip_physical{38.0}=0x1
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phy_chain_tx_polarity_flip_physical{39.0}=0x1
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phy_chain_rx_polarity_flip_physical{39.0}=0x1
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phy_chain_tx_polarity_flip_physical{40.0}=0x0
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phy_chain_rx_polarity_flip_physical{40.0}=0x0
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phy_chain_tx_polarity_flip_physical{41.0}=0x0
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phy_chain_rx_polarity_flip_physical{41.0}=0x1
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phy_chain_tx_polarity_flip_physical{42.0}=0x1
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phy_chain_rx_polarity_flip_physical{42.0}=0x1
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phy_chain_tx_polarity_flip_physical{43.0}=0x1
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phy_chain_rx_polarity_flip_physical{43.0}=0x0
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phy_chain_tx_polarity_flip_physical{44.0}=0x0
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phy_chain_rx_polarity_flip_physical{44.0}=0x1
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phy_chain_tx_polarity_flip_physical{45.0}=0x1
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phy_chain_rx_polarity_flip_physical{45.0}=0x1
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phy_chain_tx_polarity_flip_physical{46.0}=0x1
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phy_chain_rx_polarity_flip_physical{46.0}=0x1
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phy_chain_tx_polarity_flip_physical{47.0}=0x0
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phy_chain_rx_polarity_flip_physical{47.0}=0x0
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phy_chain_tx_polarity_flip_physical{48.0}=0x0
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phy_chain_rx_polarity_flip_physical{48.0}=0x0
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phy_chain_tx_polarity_flip_physical{49.0}=0x0
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phy_chain_rx_polarity_flip_physical{49.0}=0x0
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phy_chain_tx_polarity_flip_physical{50.0}=0x1
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phy_chain_rx_polarity_flip_physical{50.0}=0x0
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phy_chain_tx_polarity_flip_physical{51.0}=0x1
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phy_chain_rx_polarity_flip_physical{51.0}=0x0
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phy_chain_tx_polarity_flip_physical{52.0}=0x1
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phy_chain_rx_polarity_flip_physical{52.0}=0x1
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dport_map_port_1=1
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dport_map_port_2=2
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dport_map_port_3=3
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dport_map_port_4=4
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dport_map_port_5=5
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dport_map_port_6=6
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dport_map_port_7=7
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dport_map_port_8=8
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dport_map_port_9=9
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dport_map_port_10=10
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dport_map_port_11=11
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dport_map_port_12=12
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dport_map_port_33=13
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dport_map_port_34=14
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dport_map_port_35=15
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dport_map_port_36=16
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dport_map_port_37=17
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dport_map_port_38=18
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dport_map_port_39=19
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dport_map_port_40=20
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dport_map_port_41=21
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dport_map_port_42=22
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dport_map_port_43=23
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dport_map_port_44=24
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pbmp_oversubscribe=0x7fff9fffffffffffffffe
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pbmp_xport_xe=0x7fff9fffffffffffffffe
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port_flex_enable=1
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phy_an_c73=3
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oversubscribe_mode=1
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core_clock_frequency=1525
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l2xmsg_mode=1
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l2xmsg_hostbuf_size=16384
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module_64ports=0
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#Interrupts and Parity
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max_vp_lags=0
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schan_intr_enable=0
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tdma_timeout_usec=5000000
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stable_size=0x5500000
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#Default L3 profile
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l2_mem_entries=40960
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l3_alpm_enable=2
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l3_alpm_ipv6_128b_bkt_rsvd=1
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l3_mem_entries=40960
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#Tunnels
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use_all_splithorizon_groups=1
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sai_tunnel_support=1
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bcm_tunnel_term_compatible_mode=1
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#RIOT Enable
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riot_enable=1
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riot_overlay_l3_intf_mem_size=4096
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riot_overlay_l3_egress_mem_size=32768
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l3_ecmp_levels=2
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riot_overlay_ecmp_resilient_hash_size=16384
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#sai_preinit_cmd_file=/usr/share/sonic/hwsku/sai_preinit_cmd.soc
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#New Additions
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pfc_deadlock_seq_control=1
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#Common configs from broadcom/x86_64-broadcom_common/x86_64-broadcom_b77/broadcom-sonic-td3.config.bcm (Lower version of Td3 (0xb771))
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mem_cache_enable=0
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ifp_inports_support_enable=1
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ipv6_lpm_128b_enable=0x1
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l3_max_ecmp_mode=1
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lpm_scaling_enable=0
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bcm_num_cos=10
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default_cpu_tx_queue=9
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mmu_lossless=0
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host_as_route_disable=1
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sai_eapp_config_file=/etc/broadcom/eapps_cfg.json
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sai_fast_convergence_support=1
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flow_init_mode=1
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sai_load_hw_config=/usr/lib/cancun/
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# Reduced Trap Group QSET for BRCM Sonic
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