e286869b24
- Why I did it 1. Update Mellanox HW-MGMT package to newer version V.7.0030.1011 2. Replace the SONiC PMON Thermal control algorithm with the one inside the HW-MGMT package on all Nvidia platforms 3. Support Spectrum-4 systems - How I did it 1. Update the HW-MGMT package version number and submodule pointer 2. Remove the thermal control algorithm implementation from Mellanox platform API 3. Revise the patch to HW-MGMT package which will disable HW-MGMT from running on SIMX 4. Update the downstream kernel patch list Signed-off-by: Kebo Liu <kebol@nvidia.com>
33 lines
1.2 KiB
Diff
33 lines
1.2 KiB
Diff
From 21cafe13f2452a7c41c623dc63af9cbaa301108d Mon Sep 17 00:00:00 2001
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From: Michael Shych <michaelsh@nvidia.com>
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Date: Wed, 28 Jun 2023 12:23:43 +0000
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Subject: [PATCH v1 1/1] platform: mellanox: mlx-platform: fix CPLD4 PN report.
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Add two lines from upstream commits:
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[9045512ca6cdb221cd1ed32d483eac3c30c53bed]
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[ae1aabf44bd672a07c4fa3ef56f069ed7daa7823]
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Fix PN report of CPLD4.
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Signed-off-by: Michael Shych <michaelsh@nvidia.com>
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---
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drivers/platform/mellanox/mlx-platform.c | 2 ++
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1 file changed, 2 insertions(+)
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diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
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index 00e62366b..641e7fe1f 100644
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--- a/drivers/platform/mellanox/mlx-platform.c
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+++ b/drivers/platform/mellanox/mlx-platform.c
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@@ -5605,6 +5605,8 @@ static bool mlxplat_mlxcpld_volatile_reg(struct device *dev, unsigned int reg)
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case MLXPLAT_CPLD_LPC_REG_CPLD2_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD3_PN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD3_PN1_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_CPLD4_PN_OFFSET:
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+ case MLXPLAT_CPLD_LPC_REG_CPLD4_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_PN_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_CPLD5_PN1_OFFSET:
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case MLXPLAT_CPLD_LPC_REG_RESET_GP4_OFFSET:
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--
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2.14.1
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