e286869b24
- Why I did it 1. Update Mellanox HW-MGMT package to newer version V.7.0030.1011 2. Replace the SONiC PMON Thermal control algorithm with the one inside the HW-MGMT package on all Nvidia platforms 3. Support Spectrum-4 systems - How I did it 1. Update the HW-MGMT package version number and submodule pointer 2. Remove the thermal control algorithm implementation from Mellanox platform API 3. Revise the patch to HW-MGMT package which will disable HW-MGMT from running on SIMX 4. Update the downstream kernel patch list Signed-off-by: Kebo Liu <kebol@nvidia.com>
60 lines
2.1 KiB
Diff
60 lines
2.1 KiB
Diff
From 6720a3b49d3c0bb26d18bfe651bd9101dde34fc8 Mon Sep 17 00:00:00 2001
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From: Vadim Pasternak <vadimp@nvidia.com>
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Date: Wed, 15 Mar 2023 19:23:20 +0000
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Subject: [PATCH backport v.5.10 1/3] platform: mellanox: mlx-platform: Fix
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signals polarity and latch mask
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Change polarity of chassis health and power signals and fix latch reset
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mask for L1 switch.
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Fixes: dd635e33b5c9 ("platform: mellanox: Introduce support of new Nvidia L1 switch")
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Signed-off-by: Vadim Pasternak <vadimp@nvidia.com>
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Reviewed-by: Michael Shych <michaelsh@nvidia.com>
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---
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drivers/platform/mellanox/mlx-platform.c | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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diff --git a/drivers/platform/mellanox/mlx-platform.c b/drivers/platform/mellanox/mlx-platform.c
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index fa2e539b6..2bc3720a4 100644
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--- a/drivers/platform/mellanox/mlx-platform.c
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+++ b/drivers/platform/mellanox/mlx-platform.c
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@@ -244,7 +244,7 @@
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#define MLXPLAT_CPLD_EROT_MASK GENMASK(1, 0)
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#define MLXPLAT_CPLD_FU_CAP_MASK GENMASK(1, 0)
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#define MLXPLAT_CPLD_PWR_BUTTON_MASK BIT(0)
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-#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(5)
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+#define MLXPLAT_CPLD_LATCH_RST_MASK BIT(6)
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#define MLXPLAT_CPLD_THERMAL1_PDB_MASK BIT(3)
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#define MLXPLAT_CPLD_THERMAL2_PDB_MASK BIT(4)
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#define MLXPLAT_CPLD_INTRUSION_MASK BIT(6)
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@@ -2631,7 +2631,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = {
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.reg = MLXPLAT_CPLD_LPC_REG_PWRB_OFFSET,
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.mask = MLXPLAT_CPLD_PWR_BUTTON_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_pwr_events_items_data),
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- .inversed = 0,
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+ .inversed = 1,
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.health = false,
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},
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{
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@@ -2640,7 +2640,7 @@ static struct mlxreg_core_item mlxplat_mlxcpld_l1_switch_events_items[] = {
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.reg = MLXPLAT_CPLD_LPC_REG_BRD_OFFSET,
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.mask = MLXPLAT_CPLD_L1_CHA_HEALTH_MASK,
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.count = ARRAY_SIZE(mlxplat_mlxcpld_l1_switch_health_events_items_data),
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- .inversed = 0,
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+ .inversed = 1,
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.health = false,
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.ind = 8,
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},
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@@ -3958,7 +3958,7 @@ static struct mlxreg_core_data mlxplat_mlxcpld_default_ng_regs_io_data[] = {
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{
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.label = "latch_reset",
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.reg = MLXPLAT_CPLD_LPC_REG_GP1_OFFSET,
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- .mask = GENMASK(7, 0) & ~BIT(5),
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+ .mask = GENMASK(7, 0) & ~BIT(6),
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.mode = 0200,
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},
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{
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--
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2.20.1
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