bc2a13136a
BCMSAI 4.3.0.10, 6.5.21 SDK release with enhancements and fixes for vxlan, TD3 MMU, TD4-X9 EA support, etc.
551 lines
13 KiB
C
551 lines
13 KiB
C
/*! \file ngbde_intr.c
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*
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* API for controlling a thread-based user-mode interrupt handler.
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*
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*/
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/*
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* $Copyright: Copyright 2018-2020 Broadcom. All rights reserved.
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* The term 'Broadcom' refers to Broadcom Inc. and/or its subsidiaries.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* version 2 as published by the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* A copy of the GNU General Public License version 2 (GPLv2) can
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* be found in the LICENSES folder.$
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*/
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#include <ngbde.h>
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/*! \cond */
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static int intr_debug = 0;
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module_param(intr_debug, int, 0);
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MODULE_PARM_DESC(intr_debug,
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"Interrupt debug output enable (default 0).");
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/*! \endcond */
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static int
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ngbde_intr_shared_write32(struct ngbde_dev_s *sd, struct ngbde_intr_ctrl_s *ic,
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uint32_t reg_offs, uint32_t reg_val, uint32_t shr_mask)
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{
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unsigned long flags;
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struct ngbde_shr_reg_s *sr;
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int idx;
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sr = NULL;
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for (idx = 0; idx < NGBDE_NUM_INTR_SHR_REGS_MAX; idx++) {
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if (sd->intr_shr_reg[idx].reg_offs == 0) {
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/* If not found, then we add a new entry */
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sd->intr_shr_reg[idx].reg_offs = reg_offs;
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}
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if (sd->intr_shr_reg[idx].reg_offs == reg_offs) {
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sr = &sd->intr_shr_reg[idx];
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break;
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}
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}
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if (sr == NULL) {
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return -1;
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}
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spin_lock_irqsave(&sd->lock, flags);
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sr->cur_val &= ~shr_mask;
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sr->cur_val |= (reg_val & shr_mask);
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NGBDE_IOWRITE32(sr->cur_val, ic->iomem + reg_offs);
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spin_unlock_irqrestore(&sd->lock, flags);
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return 0;
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}
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/*!
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* \brief Interrupt handler for user mode thread.
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*
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* This function will determine whether a user-mode interrupt has
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* occurred by reading the configured interrupt status and mask
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* registers.
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*
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* If an interrupt has occurred, any waiting user-mode thread is woken
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* up.
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*
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* \param [in] ic Interrupt control information.
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*
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* \retval 1 One or more user mode interrupts occurred.
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* \retval 0 No user mode interrupts occurred.
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*/
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static int
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ngbde_user_isr(ngbde_intr_ctrl_t *ic)
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{
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int idx;
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int active_interrupts = 0;
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uint32_t stat = 0, mask = 0;
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uint32_t kmask;
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/* Check if any enabled interrupts are active */
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for (idx = 0; idx < ic->num_regs; idx++) {
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ngbde_irq_reg_t *ir = &ic->regs[idx];
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/* Get mask of all kernel interrupt sources for this register address */
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kmask = ir->kmask;
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stat = NGBDE_IOREAD32(&ic->iomem[ir->status_reg]);
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mask = NGBDE_IOREAD32(&ic->iomem[ir->mask_reg]);
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if (stat & mask & ~kmask) {
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active_interrupts = 1;
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break;
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}
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}
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/* No active interrupts to service */
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if (!active_interrupts) {
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return 0;
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}
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/* Disable (mask off) all interrupts */
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for (idx = 0; idx < ic->num_regs; idx++) {
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ngbde_irq_reg_t *ir = &ic->regs[idx];
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/* Get mask of all kernel interrupt sources for this register address */
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kmask = ir->kmask;
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if (kmask == 0xffffffff) {
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/* Kernel driver owns all interrupts in this register */
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continue;
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} else if (kmask) {
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/* Synchronized write */
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struct ngbde_dev_s *sd = ngbde_swdev_get(ic->kdev);
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if (ngbde_intr_shared_write32(sd, ic, ir->mask_reg, 0, ~kmask) < 0) {
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printk(KERN_WARNING
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"%s: Failed to write shared register for device %d\n",
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MOD_NAME, ic->kdev);
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/* Fall back to normal write to ensure interrupts are masked */
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NGBDE_IOWRITE32(0, &ic->iomem[ir->mask_reg]);
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}
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} else {
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NGBDE_IOWRITE32(0, &ic->iomem[ir->mask_reg]);
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}
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}
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atomic_set(&ic->run_user_thread, 1);
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wake_up_interruptible(&ic->user_thread_wq);
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return 1;
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}
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/*!
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* \brief Interrupt handler for kernel driver.
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*
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* Typically used by the KNET driver.
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*
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* \param [in] ic Interrupt control information.
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*
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* \retval 1 One or more kernel mode interrupts occurred.
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* \retval 0 No kernel mode interrupts occurred.
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*/
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static int
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ngbde_kernel_isr(ngbde_intr_ctrl_t *ic)
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{
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if (ic->isr_func) {
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return ic->isr_func(ic->isr_data);
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}
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return 0;
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}
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/*!
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* \brief Acknowledge interrupt
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*
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* \param [in] data Interrupt control information
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*
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* \retval 0
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*/
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static int
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ngbde_intr_ack(ngbde_intr_ctrl_t *ic)
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{
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struct ngbde_dev_s *sd = ngbde_swdev_get(ic->kdev);
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struct ngbde_intr_ack_reg_s *ar = &ic->intr_ack;
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if (sd->use_msi) {
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if (ar->flags & NGBDE_INTR_ACK_F_PAXB) {
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NGBDE_IOWRITE32(ar->ack_val, &sd->paxb_mem[ar->ack_reg]);
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} else {
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NGBDE_IOWRITE32(ar->ack_val, &sd->pio_mem[ar->ack_reg]);
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}
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}
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return 0;
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}
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/*!
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* \brief Linux ISR
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*
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* Will call the user-mode interrupts handler and optionally also a
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* kernel mode interrupt handler (typically KNET).
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*
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* \param [in] irq_num Interrupt vector from kernel.
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* \param [in] data Interrupt control information
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*
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* \retval IRQ_NONE Interrupt not recognized.
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* \retval IRQ_HANDLED Interrupt recognized and handled (masked off).
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*/
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static irqreturn_t
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ngbde_isr(int irq_num, void *data)
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{
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struct ngbde_intr_ctrl_s *ic = (struct ngbde_intr_ctrl_s *)data;
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irqreturn_t rv = IRQ_NONE;
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ngbde_intr_ack(ic);
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if (ngbde_user_isr(ic)) {
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rv = IRQ_HANDLED;
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}
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if (ngbde_kernel_isr(ic)) {
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rv = IRQ_HANDLED;
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}
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return rv;
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}
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int
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ngbde_intr_connect(int kdev, unsigned int irq_num)
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{
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struct ngbde_dev_s *sd;
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struct ngbde_intr_ctrl_s *ic;
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unsigned long irq_flags;
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sd = ngbde_swdev_get(kdev);
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if (!sd) {
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return -1;
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}
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if (irq_num >= NGBDE_NUM_IRQS_MAX) {
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return -1;
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}
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ic = &sd->intr_ctrl[irq_num];
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if (ic->irq_active) {
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return 0;
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}
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if (sd->irq_line >= 0) {
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if (sd->pio_mem == NULL) {
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printk(KERN_WARNING "%s: No memory-mapped I/O for device %d\n",
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MOD_NAME, kdev);
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return -1;
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}
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ic->kdev = kdev;
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ic->iomem = sd->pio_mem;
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if (sd->iio_mem) {
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if (intr_debug) {
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printk("INTR: Using dedicated interrupt controller\n");
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}
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ic->iomem = sd->iio_mem;
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}
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init_waitqueue_head(&ic->user_thread_wq);
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atomic_set(&ic->run_user_thread, 0);
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irq_flags = IRQF_SHARED;
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ic->irq_vect = sd->irq_line;
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/*
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* The pci_enable_msi function must be called after enabling
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* BAR0_PAXB_OARR_FUNC0_MSI_PAGE, otherwise, MSI interrupts
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* cannot be triggered!
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*/
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if (sd->use_msi) {
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if (pci_enable_msi(sd->pci_dev) == 0) {
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irq_flags = 0;
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ic->irq_vect = sd->pci_dev->irq;
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if (intr_debug) {
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printk("INTR: Enabled MSI interrupts\n");
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}
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} else {
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printk(KERN_WARNING "%s: Failed to enable MSI for device %d\n",
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MOD_NAME, kdev);
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sd->use_msi = 0;
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}
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}
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if (intr_debug) {
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printk("INTR: Request IRQ %d\n", ic->irq_vect);
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}
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if (request_irq(ic->irq_vect, ngbde_isr, irq_flags, MOD_NAME, ic) < 0) {
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printk(KERN_WARNING "%s: Could not get IRQ %d for device %d\n",
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MOD_NAME, ic->irq_vect, kdev);
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return -1;
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}
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ic->irq_active = 1;
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}
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return 0;
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}
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int
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ngbde_intr_disconnect(int kdev, unsigned int irq_num)
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{
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struct ngbde_dev_s *sd;
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struct ngbde_intr_ctrl_s *ic;
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sd = ngbde_swdev_get(kdev);
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if (!sd) {
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return -1;
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}
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if (irq_num >= NGBDE_NUM_IRQS_MAX) {
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return -1;
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}
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ic = &sd->intr_ctrl[irq_num];
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if (!ic->irq_active) {
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return 0;
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}
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if (ic->isr_func) {
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printk(KERN_WARNING "%s: Disconnecting IRQ %d blocked by kernel ISR\n",
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MOD_NAME, irq_num);
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return 0;
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}
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if (ic->irq_vect >= 0) {
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free_irq(ic->irq_vect, ic);
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if (sd->use_msi) {
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pci_disable_msi(sd->pci_dev);
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}
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ic->irq_active = 0;
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}
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return 0;
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}
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void
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ngbde_intr_cleanup(void)
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{
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struct ngbde_dev_s *swdev;
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unsigned int num_swdev, idx, irq_num;
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ngbde_swdev_get_all(&swdev, &num_swdev);
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for (idx = 0; idx < num_swdev; idx++) {
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for (irq_num = 0; irq_num < NGBDE_NUM_IRQS_MAX; irq_num++) {
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ngbde_intr_disconnect(idx, irq_num);
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}
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}
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}
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int
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ngbde_intr_wait(int kdev, unsigned int irq_num)
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{
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struct ngbde_dev_s *sd;
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struct ngbde_intr_ctrl_s *ic;
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sd = ngbde_swdev_get(kdev);
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if (!sd) {
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return -1;
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}
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if (irq_num >= NGBDE_NUM_IRQS_MAX) {
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return -1;
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}
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ic = &sd->intr_ctrl[irq_num];
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if (!ic->irq_active) {
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return 0;
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}
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wait_event_interruptible(ic->user_thread_wq,
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atomic_read(&ic->run_user_thread) != 0);
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atomic_set(&ic->run_user_thread, 0);
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return 0;
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}
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int
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ngbde_intr_stop(int kdev, unsigned int irq_num)
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{
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struct ngbde_dev_s *sd;
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struct ngbde_intr_ctrl_s *ic;
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sd = ngbde_swdev_get(kdev);
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if (!sd) {
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return -1;
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}
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if (irq_num >= NGBDE_NUM_IRQS_MAX) {
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return -1;
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}
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ic = &sd->intr_ctrl[irq_num];
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if (!ic->irq_active) {
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return 0;
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}
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/* Wake up user thread */
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atomic_set(&ic->run_user_thread, 1);
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wake_up_interruptible(&ic->user_thread_wq);
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return 0;
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}
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int
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ngbde_intr_regs_clr(int kdev, unsigned int irq_num)
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{
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struct ngbde_dev_s *sd;
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struct ngbde_intr_ctrl_s *ic;
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sd = ngbde_swdev_get(kdev);
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if (!sd) {
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return -1;
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}
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if (irq_num >= NGBDE_NUM_IRQS_MAX) {
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return -1;
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}
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ic = &sd->intr_ctrl[irq_num];
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if (ic->irq_active) {
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/* Do not clear configuration with interrupt connected */
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return 0;
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}
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ic->num_regs = 0;
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memset(ic->regs, 0, sizeof(ic->regs));
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return 0;
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}
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int
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ngbde_intr_reg_add(int kdev, unsigned int irq_num,
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struct ngbde_irq_reg_s *ireg)
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{
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struct ngbde_dev_s *sd;
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struct ngbde_intr_ctrl_s *ic;
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struct ngbde_irq_reg_s *ir;
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unsigned int idx;
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sd = ngbde_swdev_get(kdev);
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if (!sd) {
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return -1;
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}
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if (irq_num >= NGBDE_NUM_IRQS_MAX) {
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return -1;
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}
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ic = &sd->intr_ctrl[irq_num];
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if (ic->irq_active) {
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/*
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* If the interrupt is connected, then we only update the
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* kernel mask for existing entries.
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*/
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for (idx = 0; idx < ic->num_regs; idx++) {
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ir = &ic->regs[idx];
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if (ir->status_reg == ireg->status_reg &&
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ir->mask_reg == ireg->mask_reg) {
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ir->kmask = ireg->kmask;
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if (intr_debug) {
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printk("INTR: Updating interrupt register "
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"0x%08x/0x%08x (0x%08x)\n",
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ir->status_reg, ir->mask_reg, ir->kmask);
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}
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return 0;
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}
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}
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return -1;
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}
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if (ic->num_regs >= NGBDE_NUM_IRQ_REGS_MAX) {
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return -1;
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}
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ir = &ic->regs[ic->num_regs++];
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memcpy(ir, ireg, sizeof (*ir));
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if (intr_debug) {
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printk("INTR: Adding interrupt register 0x%08x/0x%08x (0x%08x)\n",
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ir->status_reg, ir->mask_reg, ir->kmask);
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}
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return ic->num_regs;
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}
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int
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ngbde_intr_ack_reg_add(int kdev, unsigned int irq_num,
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struct ngbde_intr_ack_reg_s *ackreg)
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{
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struct ngbde_dev_s *sd;
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struct ngbde_intr_ctrl_s *ic;
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struct ngbde_intr_ack_reg_s *ar;
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sd = ngbde_swdev_get(kdev);
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if (!sd) {
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return -1;
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}
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if (irq_num >= NGBDE_NUM_IRQS_MAX) {
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return -1;
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}
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ic = &sd->intr_ctrl[irq_num];
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if (ic->irq_active) {
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/* Ignore request if interrupt is connected */
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return 0;
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}
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ar = &ic->intr_ack;
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memcpy(ar, ackreg, sizeof (*ar));
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if (intr_debug) {
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printk("INTR: Adding interrupt ACK register 0x%08x/0x%08x (0x%08x)\n",
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ar->ack_reg, ar->ack_val, ar->flags);
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}
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return 0;
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}
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int
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ngbde_intr_mask_write(int kdev, unsigned int irq_num, int kapi,
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uint32_t status_reg, uint32_t mask_val)
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{
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struct ngbde_dev_s *sd;
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struct ngbde_intr_ctrl_s *ic;
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struct ngbde_irq_reg_s *ir;
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unsigned int idx;
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uint32_t bmask;
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sd = ngbde_swdev_get(kdev);
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if (!sd) {
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return -1;
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}
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if (irq_num >= NGBDE_NUM_IRQS_MAX) {
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return -1;
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}
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ic = &sd->intr_ctrl[irq_num];
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ir = ic->regs;
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for (idx = 0; idx < ic->num_regs; idx++) {
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if (ir->status_reg == status_reg) {
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bmask = kapi ? ir->kmask : ~ir->kmask;
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ngbde_intr_shared_write32(sd, ic, ir->mask_reg, mask_val, bmask);
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return 0;
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}
|
|
ir++;
|
|
}
|
|
|
|
return -1;
|
|
}
|