198 lines
6.8 KiB
C
198 lines
6.8 KiB
C
/*
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*
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* S9100-32X I2C CPLD driver header file
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*
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* Copyright (C) 2017 Ingrasys, Inc.
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* Wade He <feng.lee.usa@ingrasys.com>
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*
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* This program is free software: you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation, either version 2 of the License, or
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* (at your option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef I2C_CPLD_H
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#define I2C_CPLD_H
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// remove debug before release
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#define DEBUG
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/* CPLD device index value */
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enum cpld_id {
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i2c_cpld
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};
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/* port number on CPLD */
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#define CPLD_1_PORT_NUM 12
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#define CPLD_2_PORT_NUM 13
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/* QSFP port number */
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#define QSFP_MAX_PORT_NUM 64
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#define QSFP_MIN_PORT_NUM 1
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/* SFP+ port number */
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#define SFP_MAX_PORT_NUM 2
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#define SFP_MIN_PORT_NUM 1
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/* CPLD registers */
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#define CPLD_BOARD_TYPE_REG 0x0
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#define CPLD_EXT_BOARD_TYPE_REG 0x7
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#define CPLD_VERSION_REG 0x1
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#define CPLD_PW_GOOD_REG 0x2
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#define CPLD_PW_ABS_REG 0x3
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/* bit definition for register value */
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enum CPLD_RESET_CONTROL_BITS {
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CPLD_RESET_CONTROL_SWRST_BIT,
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CPLD_RESET_CONTROL_CP2104RST_BIT,
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CPLD_RESET_CONTROL_82P33814RST_BIT,
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CPLD_RESET_CONTROL_BMCRST_BIT,
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};
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/* bit field structure for register value */
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struct cpld_reg_board_type_t {
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u8 build_rev:2;
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u8 hw_rev:2;
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u8 board_id:4;
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};
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struct cpld_reg_version_t {
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u8 revision:6;
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u8 release:1;
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u8 reserve:1;
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};
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struct cpld_reg_pw_good_t {
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u8 reserve1:3;
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u8 psu1:1;
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u8 psu2:1;
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u8 reserve2:3;
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};
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struct cpld_reg_pw_abs_t {
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u8 psu1:1;
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u8 psu2:1;
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u8 reserve:6;
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};
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/* common manipulation */
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#define INVALID(i, min, max) ((i < min) || (i > max) ? 1u : 0u)
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#define READ_BIT(val, bit) ((0u == (val & (1<<bit))) ? 0u : 1u)
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#define SET_BIT(val, bit) (val |= (1 << bit))
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#define CLEAR_BIT(val, bit) (val &= ~(1 << bit))
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#define TOGGLE_BIT(val, bit) (val ^= (1 << bit))
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#define _BIT(n) (1<<(n))
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#define _BIT_MASK(len) (BIT(len)-1)
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/* bitfield of register manipulation */
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#define READ_BF(bf_struct, val, bf_name, bf_value) \
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(bf_value = ((struct bf_struct *)&val)->bf_name)
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#define READ_BF_1(bf_struct, val, bf_name, bf_value) \
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bf_struct bf; \
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bf.data = val; \
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bf_value = bf.bf_name
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#define BOARD_TYPE_BUILD_REV_GET(val, res) \
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READ_BF(cpld_reg_board_type_t, val, build_rev, res)
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#define BOARD_TYPE_HW_REV_GET(val, res) \
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READ_BF(cpld_reg_board_type_t, val, hw_rev, res)
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#define BOARD_TYPE_BOARD_ID_GET(val, res) \
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READ_BF(cpld_reg_board_type_t, val, board_id, res)
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#define CPLD_VERSION_REV_GET(val, res) \
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READ_BF(cpld_reg_version_t, val, revision, res)
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#define CPLD_VERSION_REL_GET(val, res) \
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READ_BF(cpld_reg_version_t, val, release, res)
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#define CPLD_PSU1_PW_GOOD_GET(val, res) \
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READ_BF(cpld_reg_pw_good_t, val, psu1, res)
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#define CPLD_PSU2_PW_GOOD_GET(val, res) \
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READ_BF(cpld_reg_pw_good_t, val, psu2, res)
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#define CPLD_PSU1_PW_ABS_GET(val, res) \
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READ_BF(cpld_reg_pw_abs_t, val, psu1, res)
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#define CPLD_PSU2_PW_ABS_GET(val, res) \
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READ_BF(cpld_reg_pw_abs_t, val, psu2, res)
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/* QSFP/SFP registers manipulation */
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#define QSFP_TO_CPLD_IDX(qsfp_port, cpld_index, cpld_port) \
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{ \
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if (QSFP_MIN_PORT_NUM <= qsfp_port && qsfp_port <= CPLD_1_PORT_NUM) { \
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cpld_index = cpld1; \
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cpld_port = qsfp_port - 1; \
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} else if (CPLD_1_PORT_NUM < qsfp_port \
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&& qsfp_port <= QSFP_MAX_PORT_NUM) { \
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cpld_index = cpld2 + (qsfp_port - 1 - CPLD_1_PORT_NUM) \
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/ CPLD_2_PORT_NUM; \
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cpld_port = (qsfp_port - 1 - CPLD_1_PORT_NUM) % \
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CPLD_2_PORT_NUM; \
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} else { \
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cpld_index = 0; \
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cpld_port = 0; \
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} \
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}
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#define SFP_TO_CPLD_IDX(sfp_port, cpld_index) \
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(cpld_index = sfp_port - SFP_MIN_PORT_NUM)
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#define QSFP_PORT_STATUS_REG(cpld_port) \
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(CPLD_QSFP_PORT_STATUS_BASE_REG + cpld_port)
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#define QSFP_PORT_CONFIG_REG(cpld_port) \
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(CPLD_QSFP_PORT_CONFIG_BASE_REG + cpld_port)
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#define QSFP_PORT_INT_BIT_GET(port_status_value) \
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READ_BIT(port_status_value, CPLD_QSFP_PORT_STATUS_INT_BIT)
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#define QSFP_PORT_ABS_BIT_GET(port_status_value) \
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READ_BIT(port_status_value, CPLD_QSFP_PORT_STATUS_ABS_BIT)
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#define QSFP_PORT_RESET_BIT_GET(port_config_value) \
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READ_BIT(port_config_value, CPLD_QSFP_PORT_CONFIG_RESET_BIT)
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#define QSFP_PORT_LPMODE_BIT_GET(port_config_value) \
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READ_BIT(port_config_value, CPLD_QSFP_PORT_CONFIG_LPMODE_BIT)
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#define QSFP_PORT_RESET_BIT_SET(port_config_value) \
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SET_BIT(port_config_value, CPLD_QSFP_PORT_CONFIG_RESET_BIT)
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#define QSFP_PORT_RESET_BIT_CLEAR(port_config_value) \
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CLEAR_BIT(port_config_value, CPLD_QSFP_PORT_CONFIG_RESET_BIT)
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#define QSFP_PORT_LPMODE_BIT_SET(port_config_value) \
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SET_BIT(port_config_value, CPLD_QSFP_PORT_CONFIG_LPMODE_BIT)
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#define QSFP_PORT_LPMODE_BIT_CLEAR(port_config_value) \
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CLEAR_BIT(port_config_value, CPLD_QSFP_PORT_CONFIG_LPMODE_BIT)
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#define SFP_PORT_PRESENT_BIT_GET(port_status_value) \
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READ_BIT(port_status_value, CPLD_SFP_PORT_STATUS_PRESENT_BIT)
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#define SFP_PORT_TXFAULT_BIT_GET(port_status_value) \
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READ_BIT(port_status_value, CPLD_SFP_PORT_STATUS_TXFAULT_BIT)
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#define SFP_PORT_RXLOS_BIT_GET(port_status_value) \
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READ_BIT(port_status_value, CPLD_SFP_PORT_STATUS_RXLOS_BIT)
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#define SFP_PORT_TXDIS_BIT_GET(port_status_value) \
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READ_BIT(port_status_value, CPLD_SFP_PORT_CONFIG_TXDIS_BIT)
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#define SFP_PORT_RS_BIT_GET(port_config_value) \
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READ_BIT(port_config_value, CPLD_SFP_PORT_CONFIG_RS_BIT)
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#define SFP_PORT_TS_BIT_GET(port_config_value) \
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READ_BIT(port_config_value, CPLD_SFP_PORT_CONFIG_TS_BIT)
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#define SFP_PORT_TXDIS_BIT_SET(port_config_value) \
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SET_BIT(port_config_value, CPLD_SFP_PORT_CONFIG_TXDIS_BIT)
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#define SFP_PORT_TXDIS_BIT_CLEAR(port_config_value) \
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CLEAR_BIT(port_config_value, CPLD_SFP_PORT_CONFIG_TXDIS_BIT)
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#define SFP_PORT_RS_BIT_SET(port_config_value) \
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SET_BIT(port_config_value, CPLD_SFP_PORT_CONFIG_RS_BIT)
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#define SFP_PORT_RS_BIT_CLEAR(port_config_value) \
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CLEAR_BIT(port_config_value, CPLD_SFP_PORT_CONFIG_RS_BIT)
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#define SFP_PORT_TS_BIT_SET(port_config_value) \
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SET_BIT(port_config_value, CPLD_SFP_PORT_CONFIG_TS_BIT)
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#define SFP_PORT_TS_BIT_CLEAR(port_config_value) \
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CLEAR_BIT(port_config_value, CPLD_SFP_PORT_CONFIG_TS_BIT)
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/* CPLD access functions */
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extern int i2c_cpld_get_qsfp_port_status_val(u8 port_num);
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extern int i2c_cpld_get_qsfp_port_config_val(u8 port_num);
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extern int i2c_cpld_set_qsfp_port_config_val(u8 port_num, u8 reg_val);
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extern int i2c_cpld_get_sfp_port_status_val(u8 port_num);
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extern int i2c_cpld_get_sfp_port_config_val(u8 port_num);
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extern int i2c_cpld_set_sfp_port_config_val(u8 port_num, u8 reg_val);
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extern u8 fp_port_to_phy_port(u8 fp_port);
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#endif
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