b6efb49817
as needed by SAI 3.7 and above. Without this change Warmboot fails from 3.5 to 3.7 as Braodcoam Datastructure gets corrupted after warm-boot. Signed-off-by: Abhishek Dosi <abdosi@microsoft.com>
319 lines
9.0 KiB
Plaintext
319 lines
9.0 KiB
Plaintext
### BMS (start)
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## Global settings
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bcm_num_cos=10
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dport_map_indexed=0
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## Switch settings
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# Port number and bandwidth assignment.
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portmap_1=1:100
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portmap_5=5:100
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portmap_9=9:100
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portmap_13=13:100
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portmap_17=17:100
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portmap_21=21:100
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portmap_25=25:100
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portmap_29=29:100
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portmap_34=33:100
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portmap_38=37:100
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portmap_42=41:100
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portmap_46=45:100
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portmap_50=49:100
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portmap_54=53:100
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portmap_58=57:100
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portmap_62=61:100
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portmap_68=65:100
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portmap_72=69:100
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portmap_76=73:100
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portmap_80=77:100
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portmap_84=81:100
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portmap_88=85:100
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portmap_92=89:100
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portmap_96=93:100
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portmap_102=97:100
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portmap_106=101:100
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portmap_110=105:100
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portmap_114=109:100
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portmap_118=113:100
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portmap_122=117:100
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portmap_126=121:100
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portmap_130=125:100
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# pbmp_xport_xe is used to specify if a XPORT block is configured as xe port
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# By default, an XPORT block is treated as HG port.
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pbmp_xport_xe=0x0444444441111111104444444422222222
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# Map dport number <dport> to internal port number <port>.
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dport_map_port_0=327
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dport_map_port_1=112
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dport_map_port_5=116
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dport_map_port_9=120
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dport_map_port_13=124
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dport_map_port_17=80
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dport_map_port_21=84
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dport_map_port_25=88
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dport_map_port_29=92
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dport_map_port_34=32
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dport_map_port_38=36
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dport_map_port_42=40
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dport_map_port_46=44
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dport_map_port_50=0
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dport_map_port_54=4
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dport_map_port_58=8
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dport_map_port_62=12
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dport_map_port_68=16
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dport_map_port_72=20
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dport_map_port_76=24
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dport_map_port_80=28
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dport_map_port_84=48
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dport_map_port_88=52
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dport_map_port_92=56
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dport_map_port_96=60
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dport_map_port_102=64
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dport_map_port_106=68
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dport_map_port_110=72
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dport_map_port_114=76
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dport_map_port_118=96
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dport_map_port_122=100
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dport_map_port_126=104
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dport_map_port_130=108
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# Remap XGXS rx and tx lanes to desired mapping. Four bits were used for
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# specifying each lane in the format of Lane 0 (bit 15-12), Lane 1 (bit 11-8),
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# lane 2 (bit 7-4), and lane 3 (bit 3-0).
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# For example, to reverse the tx lane mapping in 3, 2, 1, 0 order,
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xgxs_tx_lane_map_ce0=0x3210
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xgxs_rx_lane_map_ce0=0x3210
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xgxs_tx_lane_map_ce4=0x3210
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xgxs_rx_lane_map_ce4=0x2103
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xgxs_tx_lane_map_ce8=0x3210
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xgxs_rx_lane_map_ce8=0x3210
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xgxs_tx_lane_map_ce12=0x3210
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xgxs_rx_lane_map_ce12=0x2103
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xgxs_tx_lane_map_ce16=0x0123
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xgxs_rx_lane_map_ce16=0x0123
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xgxs_tx_lane_map_ce20=0x3210
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xgxs_rx_lane_map_ce20=0x2103
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xgxs_tx_lane_map_ce24=0x3210
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xgxs_rx_lane_map_ce24=0x3210
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xgxs_tx_lane_map_ce28=0x0123
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xgxs_rx_lane_map_ce28=0x1203
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xgxs_tx_lane_map_ce32=0x3210
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xgxs_rx_lane_map_ce32=0x3210
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xgxs_tx_lane_map_ce36=0x2301
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xgxs_rx_lane_map_ce36=0x3120
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xgxs_tx_lane_map_ce40=0x3210
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xgxs_rx_lane_map_ce40=0x3210
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xgxs_tx_lane_map_ce44=0x3102
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xgxs_rx_lane_map_ce44=0x2301
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xgxs_tx_lane_map_ce48=0x3210
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xgxs_rx_lane_map_ce48=0x1203
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xgxs_tx_lane_map_ce52=0x0123
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xgxs_rx_lane_map_ce52=0x3210
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xgxs_tx_lane_map_ce56=0x3210
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xgxs_rx_lane_map_ce56=0x1203
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xgxs_tx_lane_map_ce60=0x0213
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xgxs_rx_lane_map_ce60=0x3210
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xgxs_tx_lane_map_ce64=0x3120
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xgxs_rx_lane_map_ce64=0x1032
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xgxs_tx_lane_map_ce68=0x0123
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xgxs_rx_lane_map_ce68=0x3012
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xgxs_tx_lane_map_ce72=0x1230
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xgxs_rx_lane_map_ce72=0x1032
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xgxs_tx_lane_map_ce76=0x0123
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xgxs_rx_lane_map_ce76=0x3012
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xgxs_tx_lane_map_ce80=0x0213
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xgxs_rx_lane_map_ce80=0x2031
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xgxs_tx_lane_map_ce84=0x2301
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xgxs_rx_lane_map_ce84=0x3120
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xgxs_tx_lane_map_ce88=0x3210
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xgxs_rx_lane_map_ce88=0x3210
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xgxs_tx_lane_map_ce92=0x2301
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xgxs_rx_lane_map_ce92=0x3120
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xgxs_tx_lane_map_ce96=0x3210
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xgxs_rx_lane_map_ce96=0x0321
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xgxs_tx_lane_map_ce100=0x0123
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xgxs_rx_lane_map_ce100=0x1032
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xgxs_tx_lane_map_ce104=0x0123
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xgxs_rx_lane_map_ce104=0x0123
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xgxs_tx_lane_map_ce108=0x3210
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xgxs_rx_lane_map_ce108=0x2103
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xgxs_tx_lane_map_ce112=0x0123
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xgxs_rx_lane_map_ce112=0x0123
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xgxs_tx_lane_map_ce116=0x0123
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xgxs_rx_lane_map_ce116=0x1230
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xgxs_tx_lane_map_ce120=0x0123
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xgxs_rx_lane_map_ce120=0x0123
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xgxs_tx_lane_map_ce124=0x0123
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xgxs_rx_lane_map_ce124=0x1230
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# Config to describe the system Linerate or Oversubscribe mode.
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# 0: Linerate only (default).
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# 1: Oversubscribe mode (all ports will be oversub).
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# 2: Mixed mode. Check device specification for applicability. Port bitmap specified via pbmp_oversubscribe.
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oversubscribe_mode=1
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# Set the default MMU lossless behavior.
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mmu_lossless=0
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# Set preemphasis
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serdes_preemphasis_lane0_ce0=0x2c3c08
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serdes_preemphasis_lane1_ce0=0x2c3c08
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serdes_preemphasis_lane2_ce0=0x2c3c08
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serdes_preemphasis_lane3_ce0=0x2c3c08
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serdes_preemphasis_lane0_ce4=0x2c3c08
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serdes_preemphasis_lane1_ce4=0x2c3c08
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serdes_preemphasis_lane2_ce4=0x2c3c08
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serdes_preemphasis_lane3_ce4=0x2c3c08
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serdes_preemphasis_lane0_ce8=0x2c3c08
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serdes_preemphasis_lane1_ce8=0x2c3c08
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serdes_preemphasis_lane2_ce8=0x2c3c08
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serdes_preemphasis_lane3_ce8=0x2c3c08
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serdes_preemphasis_lane0_ce12=0x2c3c08
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serdes_preemphasis_lane1_ce12=0x2c3c08
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serdes_preemphasis_lane2_ce12=0x2c3c08
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serdes_preemphasis_lane3_ce12=0x2c3c08
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serdes_preemphasis_lane0_ce16=0x244408
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serdes_preemphasis_lane1_ce16=0x244408
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serdes_preemphasis_lane2_ce16=0x244408
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serdes_preemphasis_lane3_ce16=0x244408
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serdes_preemphasis_lane0_ce20=0x244408
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serdes_preemphasis_lane1_ce20=0x244408
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serdes_preemphasis_lane2_ce20=0x244408
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serdes_preemphasis_lane3_ce20=0x244408
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serdes_preemphasis_lane0_ce24=0x244408
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serdes_preemphasis_lane1_ce24=0x244408
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serdes_preemphasis_lane2_ce24=0x244408
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serdes_preemphasis_lane3_ce24=0x244408
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serdes_preemphasis_lane0_ce28=0x244408
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serdes_preemphasis_lane1_ce28=0x244408
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serdes_preemphasis_lane2_ce28=0x244408
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serdes_preemphasis_lane3_ce28=0x244408
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serdes_preemphasis_lane0_ce32=0x2c3c08
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serdes_preemphasis_lane1_ce32=0x2c3c08
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serdes_preemphasis_lane2_ce32=0x2c3c08
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serdes_preemphasis_lane3_ce32=0x2c3c08
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serdes_preemphasis_lane0_ce36=0x2c3c08
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serdes_preemphasis_lane1_ce36=0x2c3c08
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serdes_preemphasis_lane2_ce36=0x2c3c08
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serdes_preemphasis_lane3_ce36=0x2c3c08
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serdes_preemphasis_lane0_ce40=0x2c3c08
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serdes_preemphasis_lane1_ce40=0x2c3c08
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serdes_preemphasis_lane2_ce40=0x2c3c08
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serdes_preemphasis_lane3_ce40=0x2c3c08
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serdes_preemphasis_lane0_ce44=0x244408
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serdes_preemphasis_lane1_ce44=0x244408
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serdes_preemphasis_lane2_ce44=0x244408
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serdes_preemphasis_lane3_ce44=0x244408
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serdes_preemphasis_lane0_ce48=0x244408
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serdes_preemphasis_lane1_ce48=0x244408
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serdes_preemphasis_lane2_ce48=0x244408
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serdes_preemphasis_lane3_ce48=0x244408
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serdes_preemphasis_lane0_ce52=0x244408
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serdes_preemphasis_lane1_ce52=0x244408
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serdes_preemphasis_lane2_ce52=0x244408
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serdes_preemphasis_lane3_ce52=0x244408
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serdes_preemphasis_lane0_ce56=0x244408
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serdes_preemphasis_lane1_ce56=0x244408
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serdes_preemphasis_lane2_ce56=0x244408
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serdes_preemphasis_lane3_ce56=0x244408
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serdes_preemphasis_lane0_ce60=0x244408
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serdes_preemphasis_lane1_ce60=0x244408
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serdes_preemphasis_lane2_ce60=0x244408
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serdes_preemphasis_lane3_ce60=0x244408
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serdes_preemphasis_lane0_ce64=0x244408
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serdes_preemphasis_lane1_ce64=0x244408
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serdes_preemphasis_lane2_ce64=0x244408
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serdes_preemphasis_lane3_ce64=0x244408
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serdes_preemphasis_lane0_ce68=0x244408
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serdes_preemphasis_lane1_ce68=0x244408
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serdes_preemphasis_lane2_ce68=0x244408
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serdes_preemphasis_lane3_ce68=0x244408
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serdes_preemphasis_lane0_ce72=0x244408
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serdes_preemphasis_lane1_ce72=0x244408
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serdes_preemphasis_lane2_ce72=0x244408
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serdes_preemphasis_lane3_ce72=0x244408
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serdes_preemphasis_lane0_ce76=0x244408
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serdes_preemphasis_lane1_ce76=0x244408
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serdes_preemphasis_lane2_ce76=0x244408
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serdes_preemphasis_lane3_ce76=0x244408
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serdes_preemphasis_lane0_ce80=0x244408
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serdes_preemphasis_lane1_ce80=0x244408
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serdes_preemphasis_lane2_ce80=0x244408
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serdes_preemphasis_lane3_ce80=0x244408
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serdes_preemphasis_lane0_ce84=0x2c3c08
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serdes_preemphasis_lane1_ce84=0x2c3c08
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serdes_preemphasis_lane2_ce84=0x2c3c08
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serdes_preemphasis_lane3_ce84=0x2c3c08
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serdes_preemphasis_lane0_ce88=0x2c3c08
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serdes_preemphasis_lane1_ce88=0x2c3c08
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serdes_preemphasis_lane2_ce88=0x2c3c08
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serdes_preemphasis_lane3_ce88=0x2c3c08
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serdes_preemphasis_lane0_ce92=0x2c3c08
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serdes_preemphasis_lane1_ce92=0x2c3c08
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serdes_preemphasis_lane2_ce92=0x2c3c08
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serdes_preemphasis_lane3_ce92=0x2c3c08
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serdes_preemphasis_lane0_ce96=0x244408
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serdes_preemphasis_lane1_ce96=0x244408
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serdes_preemphasis_lane2_ce96=0x244408
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serdes_preemphasis_lane3_ce96=0x244408
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serdes_preemphasis_lane0_ce100=0x244408
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serdes_preemphasis_lane1_ce100=0x244408
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serdes_preemphasis_lane2_ce100=0x244408
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serdes_preemphasis_lane3_ce100=0x244408
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serdes_preemphasis_lane0_ce104=0x244408
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serdes_preemphasis_lane1_ce104=0x244408
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serdes_preemphasis_lane2_ce104=0x244408
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serdes_preemphasis_lane3_ce104=0x244408
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serdes_preemphasis_lane0_ce108=0x244408
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serdes_preemphasis_lane1_ce108=0x244408
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serdes_preemphasis_lane2_ce108=0x244408
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serdes_preemphasis_lane3_ce108=0x244408
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serdes_preemphasis_lane0_ce112=0x2c3c08
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serdes_preemphasis_lane1_ce112=0x2c3c08
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serdes_preemphasis_lane2_ce112=0x2c3c08
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serdes_preemphasis_lane3_ce112=0x2c3c08
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serdes_preemphasis_lane0_ce116=0x2c3c08
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serdes_preemphasis_lane1_ce116=0x2c3c08
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serdes_preemphasis_lane2_ce116=0x2c3c08
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serdes_preemphasis_lane3_ce116=0x2c3c08
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serdes_preemphasis_lane0_ce120=0x2c3c08
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serdes_preemphasis_lane1_ce120=0x2c3c08
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serdes_preemphasis_lane2_ce120=0x2c3c08
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serdes_preemphasis_lane3_ce120=0x2c3c08
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serdes_preemphasis_lane0_ce124=0x2c3c08
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serdes_preemphasis_lane1_ce124=0x2c3c08
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serdes_preemphasis_lane2_ce124=0x2c3c08
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serdes_preemphasis_lane3_ce124=0x2c3c08
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### BMS (end) |