186e1b9b57
This change introduces dynamic port breakout (DPB) for Arista 7050 QX32 model by adding a new SKU suffixed with `-Flex`. The breakout configuration allowed is the same as in mainline Arista EOS, i.e. 24 first ports are allowed to be used in 4x10G in addition to the default 40G mode. The last 8 ports are fixed to 40G. This is due to ASIC limitations of a total of 104 max ports. **NOTE**: As described in https://github.com/aristanetworks/sonic/issues/30#issuecomment-820584113 front panel LEDs are likely not working when operating in breakout mode. It is not clear if the LEDs work correctly in 40G mode as I have not had a chance to physically inspect the switch with this patch. Signed-off-by: Christian Svensson <blue@cmd.nu>
1009 lines
28 KiB
Plaintext
1009 lines
28 KiB
Plaintext
#/******************************************************************************
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# *
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# * File: config.bcm.cloverdales (7050-QX32)
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# * Name:
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# *
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# * Description: This file contains SDK properties for an Arista
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# * Cloverdales platform.
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# *
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# *-----------------------------------------------------------------------------
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# ******************************************************************************/
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####################################################################
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# BCM Config file for Cloverdale platform
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# - Dynamic Port Breakout Portmode (24x 40G/4x10G + 8x 40G)
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# Old LPM only configuration
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# l2_mem_entries=163840
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# l3_mem_entries=90112
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# l3_alpm_enable=0
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# ipv6_lpm_128b_enable=0
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#
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# ALPM enable
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l3_alpm_enable=2
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ipv6_lpm_128b_enable=1
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l2_mem_entries=32768
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l3_mem_entries=16384
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# From old config file
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os=unix
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higig2_hdr_mode=1
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# Parity
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parity_correction=1
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parity_enable=1
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stat_if_parity_enable=0
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# l2 thread related config vars
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l2xmsg_hostbuf_size=8192
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l2xmsg_mode=1
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bcm_num_cos=10
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bcm_stat_interval=2000000
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lls_num_l2uc=12
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max_vp_lags=0
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miim_intr_enable=0
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mmu_lossless=0
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module_64ports=0
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schan_intr_enable=0
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stable_size=0x2000000
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tdma_timeout_usec=5000000
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# for GLC transceiver
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phy_an_c73=0x0
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phy_an_c37=0x3
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###########################
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#port_init_speed_xe=40000
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#port_init_speed_xe.0=40000
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#load_firmware=0x0102
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load_firmware.0=2
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#########################
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# All ports are in oversubscription mode
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pbmp_oversubscribe=0x1fffffffffffffffffffffffffe
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pbmp_xport_xe.0=0x1fffffffffffffffffffffffffe
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phy_ext_rom_boot.0=0
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port_init_cl72_hg.0=0x11
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xgxs_lcpll_xtal_refclk.0=1
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##########################################
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#skip_L2_USER_ENTRY=0
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phy_aux_voltage_enable=1
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###############################
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serdes_fiber_pref=1
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###############################
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mdio_output_delay.0=0x0d
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###############################
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serdes_sgmii_m=0
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xgxs_lcpll_xtal_refclk=1
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xgxs_lcpll_xtal_refclk.1=1
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xgxs_lcpll_xtal_refclk.2=1
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xgxs_lcpll_xtal_refclk.3=1
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tdma_intr_enable=1
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tslam_intr_enable=1
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tslam_dma_enable.2=1
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tslam_dma_enable.3=1
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#dport_map_port=0
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#dport_map_enable=0
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#dport_map_indexed=0
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#bcm_xlate_port_enable.0=0
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#xgxs_pdetect_1=0
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table_dma_enable.0=1
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table_dma_enable.1=1
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table_dma_enable.2=1
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table_dma_enable.3=1
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serdes_driver_current_lane0_1=2
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serdes_pre_driver_current_lane0_1=2
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serdes_preemphasis_lane0_1=0x8fc0
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serdes_driver_current_lane1_1=2
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serdes_pre_driver_current_lane1_1=2
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serdes_preemphasis_lane1_1=0x8fc0
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serdes_driver_current_lane2_1=2
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serdes_pre_driver_current_lane2_1=2
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serdes_preemphasis_lane2_1=0x8fc0
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serdes_driver_current_lane3_1=2
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serdes_pre_driver_current_lane3_1=2
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serdes_preemphasis_lane3_1=0x8fc0
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serdes_driver_current_lane0_2=3
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serdes_pre_driver_current_lane0_2=2
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serdes_preemphasis_lane0_2=0x8fc0
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serdes_driver_current_lane1_2=3
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serdes_pre_driver_current_lane1_2=2
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serdes_preemphasis_lane1_2=0x8fc0
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serdes_driver_current_lane2_2=3
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serdes_pre_driver_current_lane2_2=2
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serdes_preemphasis_lane2_2=0x8fc0
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serdes_driver_current_lane3_2=3
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serdes_pre_driver_current_lane3_2=2
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serdes_preemphasis_lane3_2=0x8fc0
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serdes_driver_current_lane0_3=2
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serdes_pre_driver_current_lane0_3=2
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serdes_preemphasis_lane0_3=0x8fc0
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serdes_driver_current_lane1_3=2
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serdes_pre_driver_current_lane1_3=2
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serdes_preemphasis_lane1_3=0x8fc0
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serdes_driver_current_lane2_3=2
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serdes_pre_driver_current_lane2_3=2
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serdes_preemphasis_lane2_3=0x8fc0
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serdes_driver_current_lane3_3=2
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serdes_pre_driver_current_lane3_3=2
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serdes_preemphasis_lane3_3=0x8fc0
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serdes_driver_current_lane0_4=2
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serdes_pre_driver_current_lane0_4=2
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serdes_preemphasis_lane0_4=0x8fc0
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serdes_driver_current_lane1_4=2
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serdes_pre_driver_current_lane1_4=2
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serdes_preemphasis_lane1_4=0x8fc0
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serdes_driver_current_lane2_4=2
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serdes_pre_driver_current_lane2_4=2
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serdes_preemphasis_lane2_4=0x8fc0
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serdes_driver_current_lane3_4=2
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serdes_pre_driver_current_lane3_4=2
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serdes_preemphasis_lane3_4=0x8fc0
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serdes_driver_current_lane0_5=4
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serdes_pre_driver_current_lane0_5=4
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serdes_preemphasis_lane0_5=0xbf00
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serdes_driver_current_lane1_5=4
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serdes_pre_driver_current_lane1_5=4
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serdes_preemphasis_lane1_5=0xbf00
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serdes_driver_current_lane2_5=4
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serdes_pre_driver_current_lane2_5=4
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serdes_preemphasis_lane2_5=0xbf00
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serdes_driver_current_lane3_5=4
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serdes_pre_driver_current_lane3_5=4
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serdes_preemphasis_lane3_5=0xbf00
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serdes_driver_current_lane0_6=4
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serdes_pre_driver_current_lane0_6=4
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serdes_preemphasis_lane0_6=0xbb10
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serdes_driver_current_lane1_6=4
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serdes_pre_driver_current_lane1_6=4
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serdes_preemphasis_lane1_6=0xbb10
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serdes_driver_current_lane2_6=4
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serdes_pre_driver_current_lane2_6=4
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serdes_preemphasis_lane2_6=0xbb10
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serdes_driver_current_lane3_6=4
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serdes_pre_driver_current_lane3_6=4
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serdes_preemphasis_lane3_6=0xbb10
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serdes_driver_current_lane0_7=3
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serdes_pre_driver_current_lane0_7=3
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serdes_preemphasis_lane0_7=0xcad0
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serdes_driver_current_lane1_7=3
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serdes_pre_driver_current_lane1_7=3
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serdes_preemphasis_lane1_7=0xcad0
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serdes_driver_current_lane2_7=3
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serdes_pre_driver_current_lane2_7=3
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serdes_preemphasis_lane2_7=0xcad0
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serdes_driver_current_lane3_7=3
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serdes_pre_driver_current_lane3_7=3
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serdes_preemphasis_lane3_7=0xcad0
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serdes_driver_current_lane0_8=3
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serdes_pre_driver_current_lane0_8=3
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serdes_preemphasis_lane0_8=0xcad0
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serdes_driver_current_lane1_8=3
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serdes_pre_driver_current_lane1_8=3
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serdes_preemphasis_lane1_8=0xcad0
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serdes_driver_current_lane2_8=3
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serdes_pre_driver_current_lane2_8=3
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serdes_preemphasis_lane2_8=0xcad0
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serdes_driver_current_lane3_8=3
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serdes_pre_driver_current_lane3_8=3
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serdes_preemphasis_lane3_8=0xcad0
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serdes_driver_current_lane0_9=3
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serdes_pre_driver_current_lane0_9=3
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serdes_preemphasis_lane0_9=0xc2f0
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serdes_driver_current_lane1_9=3
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serdes_pre_driver_current_lane1_9=3
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serdes_preemphasis_lane1_9=0xc2f0
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serdes_driver_current_lane2_9=3
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serdes_pre_driver_current_lane2_9=3
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serdes_preemphasis_lane2_9=0xc2f0
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serdes_driver_current_lane3_9=3
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serdes_pre_driver_current_lane3_9=3
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serdes_preemphasis_lane3_9=0xc2f0
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serdes_driver_current_lane0_10=3
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serdes_pre_driver_current_lane0_10=3
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serdes_preemphasis_lane0_10=0xc6e0
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serdes_driver_current_lane1_10=3
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serdes_pre_driver_current_lane1_10=3
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serdes_preemphasis_lane1_10=0xc6e0
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serdes_driver_current_lane2_10=3
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serdes_pre_driver_current_lane2_10=3
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serdes_preemphasis_lane2_10=0xc6e0
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serdes_driver_current_lane3_10=3
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serdes_pre_driver_current_lane3_10=3
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serdes_preemphasis_lane3_10=0xc6e0
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serdes_driver_current_lane0_11=3
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serdes_pre_driver_current_lane0_11=3
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serdes_preemphasis_lane0_11=0xc2f0
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serdes_driver_current_lane1_11=3
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serdes_pre_driver_current_lane1_11=3
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serdes_preemphasis_lane1_11=0xc2f0
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serdes_driver_current_lane2_11=3
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serdes_pre_driver_current_lane2_11=3
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serdes_preemphasis_lane2_11=0xc2f0
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serdes_driver_current_lane3_11=3
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serdes_pre_driver_current_lane3_11=3
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serdes_preemphasis_lane3_11=0xc2f0
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serdes_driver_current_lane0_12=3
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serdes_pre_driver_current_lane0_12=3
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serdes_preemphasis_lane0_12=0xc2f0
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serdes_driver_current_lane1_12=3
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serdes_pre_driver_current_lane1_12=3
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serdes_preemphasis_lane1_12=0xc2f0
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serdes_driver_current_lane2_12=3
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serdes_pre_driver_current_lane2_12=3
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serdes_preemphasis_lane2_12=0xc2f0
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serdes_driver_current_lane3_12=3
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serdes_pre_driver_current_lane3_12=3
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serdes_preemphasis_lane3_12=0xc2f0
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serdes_driver_current_lane0_13=3
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serdes_pre_driver_current_lane0_13=3
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serdes_preemphasis_lane0_13=0xc2f0
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serdes_driver_current_lane1_13=3
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serdes_pre_driver_current_lane1_13=3
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serdes_preemphasis_lane1_13=0xc2f0
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serdes_driver_current_lane2_13=3
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serdes_pre_driver_current_lane2_13=3
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serdes_preemphasis_lane2_13=0xc2f0
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serdes_driver_current_lane3_13=3
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serdes_pre_driver_current_lane3_13=3
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serdes_preemphasis_lane3_13=0xc2f0
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serdes_driver_current_lane0_14=3
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serdes_pre_driver_current_lane0_14=3
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serdes_preemphasis_lane0_14=0xc2f0
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serdes_driver_current_lane1_14=3
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serdes_pre_driver_current_lane1_14=3
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serdes_preemphasis_lane1_14=0xc2f0
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serdes_driver_current_lane2_14=3
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serdes_pre_driver_current_lane2_14=3
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serdes_preemphasis_lane2_14=0xc2f0
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serdes_driver_current_lane3_14=3
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serdes_pre_driver_current_lane3_14=3
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serdes_preemphasis_lane3_14=0xc2f0
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serdes_driver_current_lane0_15=3
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serdes_pre_driver_current_lane0_15=3
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serdes_preemphasis_lane0_15=0xc2f0
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serdes_driver_current_lane1_15=3
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serdes_pre_driver_current_lane1_15=3
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serdes_preemphasis_lane1_15=0xc2f0
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serdes_driver_current_lane2_15=3
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serdes_pre_driver_current_lane2_15=3
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serdes_preemphasis_lane2_15=0xc2f0
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serdes_driver_current_lane3_15=3
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serdes_pre_driver_current_lane3_15=3
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serdes_preemphasis_lane3_15=0xc2f0
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serdes_driver_current_lane0_16=3
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serdes_pre_driver_current_lane0_16=3
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serdes_preemphasis_lane0_16=0xc2f0
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serdes_driver_current_lane1_16=3
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serdes_pre_driver_current_lane1_16=3
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serdes_preemphasis_lane1_16=0xc2f0
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serdes_driver_current_lane2_16=3
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serdes_pre_driver_current_lane2_16=3
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serdes_preemphasis_lane2_16=0xc2f0
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serdes_driver_current_lane3_16=3
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serdes_pre_driver_current_lane3_16=3
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serdes_preemphasis_lane3_16=0xc2f0
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serdes_driver_current_lane0_17=3
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serdes_pre_driver_current_lane0_17=3
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serdes_preemphasis_lane0_17=0xc2f0
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serdes_driver_current_lane1_17=3
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serdes_pre_driver_current_lane1_17=3
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serdes_preemphasis_lane1_17=0xc2f0
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serdes_driver_current_lane2_17=3
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serdes_pre_driver_current_lane2_17=3
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serdes_preemphasis_lane2_17=0xc2f0
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serdes_driver_current_lane3_17=3
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serdes_pre_driver_current_lane3_17=3
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serdes_preemphasis_lane3_17=0xc2f0
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serdes_driver_current_lane0_18=3
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serdes_pre_driver_current_lane0_18=3
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serdes_preemphasis_lane0_18=0xc2f0
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serdes_driver_current_lane1_18=3
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serdes_pre_driver_current_lane1_18=3
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serdes_preemphasis_lane1_18=0xc2f0
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serdes_driver_current_lane2_18=3
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serdes_pre_driver_current_lane2_18=3
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serdes_preemphasis_lane2_18=0xc2f0
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serdes_driver_current_lane3_18=3
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serdes_pre_driver_current_lane3_18=3
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serdes_preemphasis_lane3_18=0xc2f0
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serdes_driver_current_lane0_19=3
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serdes_pre_driver_current_lane0_19=3
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serdes_preemphasis_lane0_19=0xc2f0
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serdes_driver_current_lane1_19=3
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serdes_pre_driver_current_lane1_19=3
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serdes_preemphasis_lane1_19=0xc2f0
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serdes_driver_current_lane2_19=3
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serdes_pre_driver_current_lane2_19=3
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serdes_preemphasis_lane2_19=0xc2f0
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serdes_driver_current_lane3_19=3
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serdes_pre_driver_current_lane3_19=3
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serdes_preemphasis_lane3_19=0xc2f0
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serdes_driver_current_lane0_20=3
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serdes_pre_driver_current_lane0_20=3
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serdes_preemphasis_lane0_20=0xc2f0
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serdes_driver_current_lane1_20=3
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serdes_pre_driver_current_lane1_20=3
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serdes_preemphasis_lane1_20=0xc2f0
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serdes_driver_current_lane2_20=3
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serdes_pre_driver_current_lane2_20=3
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serdes_preemphasis_lane2_20=0xc2f0
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serdes_driver_current_lane3_20=3
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serdes_pre_driver_current_lane3_20=3
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serdes_preemphasis_lane3_20=0xc2f0
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serdes_driver_current_lane0_21=3
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serdes_pre_driver_current_lane0_21=3
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serdes_preemphasis_lane0_21=0xc6e0
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serdes_driver_current_lane1_21=3
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serdes_pre_driver_current_lane1_21=3
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serdes_preemphasis_lane1_21=0xc6e0
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serdes_driver_current_lane2_21=3
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serdes_pre_driver_current_lane2_21=3
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serdes_preemphasis_lane2_21=0xc6e0
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serdes_driver_current_lane3_21=3
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serdes_pre_driver_current_lane3_21=3
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serdes_preemphasis_lane3_21=0xc6e0
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serdes_driver_current_lane0_22=3
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serdes_pre_driver_current_lane0_22=3
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serdes_preemphasis_lane0_22=0xc6e0
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serdes_driver_current_lane1_22=3
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serdes_pre_driver_current_lane1_22=3
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serdes_preemphasis_lane1_22=0xc6e0
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serdes_driver_current_lane2_22=3
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serdes_pre_driver_current_lane2_22=3
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serdes_preemphasis_lane2_22=0xc6e0
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serdes_driver_current_lane3_22=3
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serdes_pre_driver_current_lane3_22=3
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serdes_preemphasis_lane3_22=0xc6e0
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serdes_driver_current_lane0_23=3
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serdes_pre_driver_current_lane0_23=3
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serdes_preemphasis_lane0_23=0xcad0
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serdes_driver_current_lane1_23=3
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serdes_pre_driver_current_lane1_23=3
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serdes_preemphasis_lane1_23=0xcad0
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serdes_driver_current_lane2_23=3
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serdes_pre_driver_current_lane2_23=3
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serdes_preemphasis_lane2_23=0xcad0
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serdes_driver_current_lane3_23=3
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serdes_pre_driver_current_lane3_23=3
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serdes_preemphasis_lane3_23=0xcad0
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serdes_driver_current_lane0_24=3
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serdes_pre_driver_current_lane0_24=3
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serdes_preemphasis_lane0_24=0xcad0
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serdes_driver_current_lane1_24=3
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serdes_pre_driver_current_lane1_24=3
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serdes_preemphasis_lane1_24=0xcad0
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serdes_driver_current_lane2_24=3
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serdes_pre_driver_current_lane2_24=3
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serdes_preemphasis_lane2_24=0xcad0
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serdes_driver_current_lane3_24=3
|
|
serdes_pre_driver_current_lane3_24=3
|
|
serdes_preemphasis_lane3_24=0xcad0
|
|
serdes_driver_current_lane0_25=5
|
|
serdes_pre_driver_current_lane0_25=5
|
|
serdes_preemphasis_lane0_25=0xc2f0
|
|
serdes_driver_current_lane1_25=5
|
|
serdes_pre_driver_current_lane1_25=5
|
|
serdes_preemphasis_lane1_25=0xc2f0
|
|
serdes_driver_current_lane2_25=5
|
|
serdes_pre_driver_current_lane2_25=5
|
|
serdes_preemphasis_lane2_25=0xc2f0
|
|
serdes_driver_current_lane3_25=5
|
|
serdes_pre_driver_current_lane3_25=5
|
|
serdes_preemphasis_lane3_25=0xc2f0
|
|
serdes_driver_current_lane0_26=5
|
|
serdes_pre_driver_current_lane0_26=5
|
|
serdes_preemphasis_lane0_26=0xc2f0
|
|
serdes_driver_current_lane1_26=5
|
|
serdes_pre_driver_current_lane1_26=5
|
|
serdes_preemphasis_lane1_26=0xc2f0
|
|
serdes_driver_current_lane2_26=5
|
|
serdes_pre_driver_current_lane2_26=5
|
|
serdes_preemphasis_lane2_26=0xc2f0
|
|
serdes_driver_current_lane3_26=5
|
|
serdes_pre_driver_current_lane3_26=5
|
|
serdes_preemphasis_lane3_26=0xc2f0
|
|
serdes_driver_current_lane0_27=5
|
|
serdes_pre_driver_current_lane0_27=5
|
|
serdes_preemphasis_lane0_27=0xc2f0
|
|
serdes_driver_current_lane1_27=5
|
|
serdes_pre_driver_current_lane1_27=5
|
|
serdes_preemphasis_lane1_27=0xc2f0
|
|
serdes_driver_current_lane2_27=5
|
|
serdes_pre_driver_current_lane2_27=5
|
|
serdes_preemphasis_lane2_27=0xc2f0
|
|
serdes_driver_current_lane3_27=5
|
|
serdes_pre_driver_current_lane3_27=5
|
|
serdes_preemphasis_lane3_27=0xc2f0
|
|
serdes_driver_current_lane0_28=8
|
|
serdes_pre_driver_current_lane0_28=6
|
|
serdes_preemphasis_lane0_28=0xc2f0
|
|
serdes_driver_current_lane1_28=8
|
|
serdes_pre_driver_current_lane1_28=6
|
|
serdes_preemphasis_lane1_28=0xc2f0
|
|
serdes_driver_current_lane2_28=8
|
|
serdes_pre_driver_current_lane2_28=6
|
|
serdes_preemphasis_lane2_28=0xc2f0
|
|
serdes_driver_current_lane3_28=8
|
|
serdes_pre_driver_current_lane3_28=6
|
|
serdes_preemphasis_lane3_28=0xc2f0
|
|
serdes_driver_current_lane0_29=2
|
|
serdes_pre_driver_current_lane0_29=2
|
|
serdes_preemphasis_lane0_29=0x8fc0
|
|
serdes_driver_current_lane1_29=2
|
|
serdes_pre_driver_current_lane1_29=2
|
|
serdes_preemphasis_lane1_29=0x8fc0
|
|
serdes_driver_current_lane2_29=2
|
|
serdes_pre_driver_current_lane2_29=2
|
|
serdes_preemphasis_lane2_29=0x8fc0
|
|
serdes_driver_current_lane3_29=2
|
|
serdes_pre_driver_current_lane3_29=2
|
|
serdes_preemphasis_lane3_29=0x8fc0
|
|
serdes_driver_current_lane0_30=2
|
|
serdes_pre_driver_current_lane0_30=2
|
|
serdes_preemphasis_lane0_30=0x8fc0
|
|
serdes_driver_current_lane1_30=2
|
|
serdes_pre_driver_current_lane1_30=2
|
|
serdes_preemphasis_lane1_30=0x8fc0
|
|
serdes_driver_current_lane2_30=2
|
|
serdes_pre_driver_current_lane2_30=2
|
|
serdes_preemphasis_lane2_30=0x8fc0
|
|
serdes_driver_current_lane3_30=2
|
|
serdes_pre_driver_current_lane3_30=2
|
|
serdes_preemphasis_lane3_30=0x8fc0
|
|
serdes_driver_current_lane0_31=2
|
|
serdes_pre_driver_current_lane0_31=2
|
|
serdes_preemphasis_lane0_31=0x8fc0
|
|
serdes_driver_current_lane1_31=2
|
|
serdes_pre_driver_current_lane1_31=2
|
|
serdes_preemphasis_lane1_31=0x8fc0
|
|
serdes_driver_current_lane2_31=2
|
|
serdes_pre_driver_current_lane2_31=2
|
|
serdes_preemphasis_lane2_31=0x8fc0
|
|
serdes_driver_current_lane3_31=2
|
|
serdes_pre_driver_current_lane3_31=2
|
|
serdes_preemphasis_lane3_31=0x8fc0
|
|
serdes_driver_current_lane0_32=2
|
|
serdes_pre_driver_current_lane0_32=2
|
|
serdes_preemphasis_lane0_32=0x8fc0
|
|
serdes_driver_current_lane1_32=2
|
|
serdes_pre_driver_current_lane1_32=2
|
|
serdes_preemphasis_lane1_32=0x8fc0
|
|
serdes_driver_current_lane2_32=2
|
|
serdes_pre_driver_current_lane2_32=2
|
|
serdes_preemphasis_lane2_32=0x8fc0
|
|
serdes_driver_current_lane3_32=2
|
|
serdes_pre_driver_current_lane3_32=2
|
|
serdes_preemphasis_lane3_32=0x8fc0
|
|
|
|
# Port {xe0, xe1, xe2, xe3} [40G, 4x10G]
|
|
phy_84328_1.0=1
|
|
phy_an_c37_1.0=3
|
|
phy_an_c73_1.0=1
|
|
phy_aux_voltage_enable_1.0=0x1
|
|
phy_ext_rom_boot_1.0=0x0
|
|
phy_line_tx_mode_1.0=1
|
|
phy_rx_polarity_flip_1.0=0x0
|
|
phy_system_tx_mode_1.0=0
|
|
phy_tx_polarity_flip_1.0=0x0
|
|
phy_xaui_rx_polarity_flip_1.0=0x0
|
|
phy_xaui_tx_polarity_flip_1.0=0x0
|
|
port_phy_addr_1.0=0x4
|
|
port_phy_clause_1.0=0x2d
|
|
port_phy_id0_1.0=0x600d
|
|
port_phy_id1_1.0=0x8500
|
|
portmap_1.0=125:40
|
|
portmap_2.0=126:10:i
|
|
portmap_3.0=127:10:i
|
|
portmap_4.0=128:10:i
|
|
serdes_firmware_mode_1.0=1
|
|
xgxs_rx_lane_map_1.0=0x0123
|
|
xgxs_tx_lane_map_1.0=0x0123
|
|
|
|
# Port {xe4, xe5, xe6, xe7} [40G, 4x10G]
|
|
phy_84328_5.0=1
|
|
phy_an_c37_5.0=3
|
|
phy_an_c73_5.0=1
|
|
phy_aux_voltage_enable_5.0=0x1
|
|
phy_ext_rom_boot_5.0=0x0
|
|
phy_line_tx_mode_5.0=1
|
|
phy_rx_polarity_flip_5.0=0x0
|
|
phy_system_tx_mode_5.0=0
|
|
phy_tx_polarity_flip_5.0=0x0
|
|
phy_xaui_rx_polarity_flip_5.0=0x0
|
|
phy_xaui_tx_polarity_flip_5.0=0x0
|
|
port_phy_addr_5.0=0x0
|
|
port_phy_clause_5.0=0x2d
|
|
port_phy_id0_5.0=0x600d
|
|
port_phy_id1_5.0=0x8500
|
|
portmap_5.0=121:40
|
|
portmap_6.0=122:10:i
|
|
portmap_7.0=123:10:i
|
|
portmap_8.0=124:10:i
|
|
serdes_firmware_mode_5.0=1
|
|
xgxs_rx_lane_map_5.0=0x0123
|
|
xgxs_tx_lane_map_5.0=0x0123
|
|
|
|
# Port {xe8, xe9, xe10, xe11} [40G, 4x10G]
|
|
phy_84328_9.0=1
|
|
phy_an_c37_9.0=3
|
|
phy_an_c73_9.0=1
|
|
phy_aux_voltage_enable_9.0=0x1
|
|
phy_ext_rom_boot_9.0=0x0
|
|
phy_line_tx_mode_9.0=1
|
|
phy_rx_polarity_flip_9.0=0x0
|
|
phy_system_tx_mode_9.0=0
|
|
phy_tx_polarity_flip_9.0=0x0
|
|
phy_xaui_rx_polarity_flip_9.0=0x0
|
|
phy_xaui_tx_polarity_flip_9.0=0x0
|
|
port_phy_addr_9.0=0x2c
|
|
port_phy_clause_9.0=0x2d
|
|
port_phy_id0_9.0=0x600d
|
|
port_phy_id1_9.0=0x8500
|
|
portmap_9.0=13:40
|
|
portmap_10.0=14:10:i
|
|
portmap_11.0=15:10:i
|
|
portmap_12.0=16:10:i
|
|
serdes_firmware_mode_9.0=1
|
|
xgxs_rx_lane_map_9.0=0x0123
|
|
xgxs_tx_lane_map_9.0=0x0123
|
|
|
|
# Port {xe12, xe13, xe14, xe15} [40G, 4x10G]
|
|
phy_84328_13.0=1
|
|
phy_an_c37_13.0=3
|
|
phy_an_c73_13.0=1
|
|
phy_aux_voltage_enable_13.0=0x1
|
|
phy_ext_rom_boot_13.0=0x0
|
|
phy_line_tx_mode_13.0=1
|
|
phy_rx_polarity_flip_13.0=0x0
|
|
phy_system_tx_mode_13.0=0
|
|
phy_tx_polarity_flip_13.0=0x0
|
|
phy_xaui_rx_polarity_flip_13.0=0x0
|
|
phy_xaui_tx_polarity_flip_13.0=0x0
|
|
port_phy_addr_13.0=0x28
|
|
port_phy_clause_13.0=0x2d
|
|
port_phy_id0_13.0=0x600d
|
|
port_phy_id1_13.0=0x8500
|
|
portmap_13.0=9:40
|
|
portmap_14.0=10:10:i
|
|
portmap_15.0=11:10:i
|
|
portmap_16.0=12:10:i
|
|
serdes_firmware_mode_13.0=1
|
|
xgxs_rx_lane_map_13.0=0x0123
|
|
xgxs_tx_lane_map_13.0=0x0123
|
|
|
|
# Port {xe16, xe17, xe18, xe19} [40G, 4x10G]
|
|
phy_an_c37_17.0=3
|
|
phy_an_c73_17.0=1
|
|
phy_xaui_rx_polarity_flip_17.0=0x0
|
|
phy_xaui_tx_polarity_flip_17.0=0x0
|
|
port_init_autoneg_17.0=0
|
|
port_phy_addr_17.0=0x7f
|
|
portmap_17.0=17:40
|
|
portmap_18.0=18:10:i
|
|
portmap_19.0=19:10:i
|
|
portmap_20.0=20:10:i
|
|
serdes_firmware_mode_17.0=2
|
|
xgxs_rx_lane_map_17.0=0x2031
|
|
xgxs_tx_lane_map_17.0=0x1302
|
|
|
|
# Port {xe20, xe21, xe22, xe23} [40G, 4x10G]
|
|
phy_an_c37_21.0=3
|
|
phy_an_c73_21.0=1
|
|
phy_xaui_rx_polarity_flip_21.0=0x0
|
|
phy_xaui_tx_polarity_flip_21.0=0x0
|
|
port_init_autoneg_21.0=0
|
|
port_phy_addr_21.0=0x7f
|
|
portmap_21.0=21:40
|
|
portmap_22.0=22:10:i
|
|
portmap_23.0=23:10:i
|
|
portmap_24.0=24:10:i
|
|
serdes_firmware_mode_21.0=2
|
|
xgxs_rx_lane_map_21.0=0x2031
|
|
xgxs_tx_lane_map_21.0=0x1302
|
|
|
|
# Port {xe24, xe25, xe26, xe27} [40G, 4x10G]
|
|
phy_an_c37_25.0=3
|
|
phy_an_c73_25.0=1
|
|
phy_xaui_rx_polarity_flip_25.0=0x0
|
|
phy_xaui_tx_polarity_flip_25.0=0x0
|
|
port_init_autoneg_25.0=0
|
|
port_phy_addr_25.0=0x7f
|
|
portmap_25.0=25:40
|
|
portmap_26.0=26:10:i
|
|
portmap_27.0=27:10:i
|
|
portmap_28.0=28:10:i
|
|
serdes_firmware_mode_25.0=2
|
|
xgxs_rx_lane_map_25.0=0x2031
|
|
xgxs_tx_lane_map_25.0=0x1302
|
|
|
|
# Port {xe28, xe29, xe30, xe31} [40G, 4x10G]
|
|
phy_an_c37_29.0=3
|
|
phy_an_c73_29.0=1
|
|
phy_xaui_rx_polarity_flip_29.0=0x0
|
|
phy_xaui_tx_polarity_flip_29.0=0x0
|
|
port_init_autoneg_29.0=0
|
|
port_phy_addr_29.0=0x7f
|
|
portmap_29.0=29:40
|
|
portmap_30.0=30:10:i
|
|
portmap_31.0=31:10:i
|
|
portmap_32.0=32:10:i
|
|
serdes_firmware_mode_29.0=2
|
|
xgxs_rx_lane_map_29.0=0x2031
|
|
xgxs_tx_lane_map_29.0=0x1302
|
|
|
|
# Port {xe32, xe33, xe34, xe35} [40G, 4x10G]
|
|
phy_an_c37_33.0=3
|
|
phy_an_c73_33.0=1
|
|
phy_xaui_rx_polarity_flip_33.0=0x0
|
|
phy_xaui_tx_polarity_flip_33.0=0x0
|
|
port_init_autoneg_33.0=0
|
|
port_phy_addr_33.0=0x7f
|
|
portmap_33.0=37:40
|
|
portmap_34.0=38:10:i
|
|
portmap_35.0=39:10:i
|
|
portmap_36.0=40:10:i
|
|
serdes_firmware_mode_33.0=2
|
|
xgxs_rx_lane_map_33.0=0x3120
|
|
xgxs_tx_lane_map_33.0=0x3120
|
|
|
|
# Port {xe36, xe37, xe38, xe39} [40G, 4x10G]
|
|
phy_an_c37_37.0=3
|
|
phy_an_c73_37.0=1
|
|
phy_xaui_rx_polarity_flip_37.0=0x0
|
|
phy_xaui_tx_polarity_flip_37.0=0x0
|
|
port_init_autoneg_37.0=0
|
|
port_phy_addr_37.0=0x7f
|
|
portmap_37.0=33:40
|
|
portmap_38.0=34:10:i
|
|
portmap_39.0=35:10:i
|
|
portmap_40.0=36:10:i
|
|
serdes_firmware_mode_37.0=2
|
|
xgxs_rx_lane_map_37.0=0x3120
|
|
xgxs_tx_lane_map_37.0=0x3120
|
|
|
|
# Port {xe40, xe41, xe42, xe43} [40G, 4x10G]
|
|
phy_an_c37_41.0=3
|
|
phy_an_c73_41.0=1
|
|
phy_xaui_rx_polarity_flip_41.0=0x0
|
|
phy_xaui_tx_polarity_flip_41.0=0x0
|
|
port_init_autoneg_41.0=0
|
|
port_phy_addr_41.0=0x7f
|
|
portmap_41.0=45:40
|
|
portmap_42.0=46:10:i
|
|
portmap_43.0=47:10:i
|
|
portmap_44.0=48:10:i
|
|
serdes_firmware_mode_41.0=2
|
|
xgxs_rx_lane_map_41.0=0x3120
|
|
xgxs_tx_lane_map_41.0=0x3120
|
|
|
|
# Port {xe44, xe45, xe46, xe47} [40G, 4x10G]
|
|
phy_an_c37_45.0=3
|
|
phy_an_c73_45.0=1
|
|
phy_xaui_rx_polarity_flip_45.0=0x0
|
|
phy_xaui_tx_polarity_flip_45.0=0x0
|
|
port_init_autoneg_45.0=0
|
|
port_phy_addr_45.0=0x7f
|
|
portmap_45.0=41:40
|
|
portmap_46.0=42:10:i
|
|
portmap_47.0=43:10:i
|
|
portmap_48.0=44:10:i
|
|
serdes_firmware_mode_45.0=2
|
|
xgxs_rx_lane_map_45.0=0x3120
|
|
xgxs_tx_lane_map_45.0=0x3120
|
|
|
|
# Port {xe48, xe49, xe50, xe51} [40G, 4x10G]
|
|
phy_an_c37_49.0=3
|
|
phy_an_c73_49.0=1
|
|
phy_xaui_rx_polarity_flip_49.0=0x0
|
|
phy_xaui_tx_polarity_flip_49.0=0x0
|
|
port_init_autoneg_49.0=0
|
|
port_phy_addr_49.0=0x7f
|
|
portmap_49.0=53:40
|
|
portmap_50.0=54:10:i
|
|
portmap_51.0=55:10:i
|
|
portmap_52.0=56:10:i
|
|
serdes_firmware_mode_49.0=2
|
|
xgxs_rx_lane_map_49.0=0x3120
|
|
xgxs_tx_lane_map_49.0=0x3120
|
|
|
|
# Port {xe52, xe53, xe54, xe55} [40G, 4x10G]
|
|
phy_an_c37_53.0=3
|
|
phy_an_c73_53.0=1
|
|
phy_xaui_rx_polarity_flip_53.0=0x0
|
|
phy_xaui_tx_polarity_flip_53.0=0x0
|
|
port_init_autoneg_53.0=0
|
|
port_phy_addr_53.0=0x7f
|
|
portmap_53.0=49:40
|
|
portmap_54.0=50:10:i
|
|
portmap_55.0=51:10:i
|
|
portmap_56.0=52:10:i
|
|
serdes_firmware_mode_53.0=2
|
|
xgxs_rx_lane_map_53.0=0x3120
|
|
xgxs_tx_lane_map_53.0=0x3120
|
|
|
|
# Port {xe56, xe57, xe58, xe59} [40G, 4x10G]
|
|
phy_an_c37_57.0=3
|
|
phy_an_c73_57.0=1
|
|
phy_xaui_rx_polarity_flip_57.0=0x0
|
|
phy_xaui_tx_polarity_flip_57.0=0x0
|
|
port_init_autoneg_57.0=0
|
|
port_phy_addr_57.0=0x7f
|
|
portmap_57.0=69:40
|
|
portmap_58.0=70:10:i
|
|
portmap_59.0=71:10:i
|
|
portmap_60.0=72:10:i
|
|
serdes_firmware_mode_57.0=2
|
|
xgxs_rx_lane_map_57.0=0x3120
|
|
xgxs_tx_lane_map_57.0=0x3120
|
|
|
|
# Port {xe60, xe61, xe62, xe63} [40G, 4x10G]
|
|
phy_an_c37_61.0=3
|
|
phy_an_c73_61.0=1
|
|
phy_xaui_rx_polarity_flip_61.0=0x0
|
|
phy_xaui_tx_polarity_flip_61.0=0x0
|
|
port_init_autoneg_61.0=0
|
|
port_phy_addr_61.0=0x7f
|
|
portmap_61.0=65:40
|
|
portmap_62.0=66:10:i
|
|
portmap_63.0=67:10:i
|
|
portmap_64.0=68:10:i
|
|
serdes_firmware_mode_61.0=2
|
|
xgxs_rx_lane_map_61.0=0x3120
|
|
xgxs_tx_lane_map_61.0=0x3120
|
|
|
|
# Port {xe64, xe65, xe66, xe67} [40G, 4x10G]
|
|
phy_an_c37_65.0=3
|
|
phy_an_c73_65.0=1
|
|
phy_xaui_rx_polarity_flip_65.0=0x0
|
|
phy_xaui_tx_polarity_flip_65.0=0x0
|
|
port_init_autoneg_65.0=0
|
|
port_phy_addr_65.0=0x7f
|
|
portmap_65.0=77:40
|
|
portmap_66.0=78:10:i
|
|
portmap_67.0=79:10:i
|
|
portmap_68.0=80:10:i
|
|
serdes_firmware_mode_65.0=2
|
|
xgxs_rx_lane_map_65.0=0x3120
|
|
xgxs_tx_lane_map_65.0=0x3120
|
|
|
|
# Port {xe68, xe69, xe70, xe71} [40G, 4x10G]
|
|
phy_an_c37_69.0=3
|
|
phy_an_c73_69.0=1
|
|
phy_xaui_rx_polarity_flip_69.0=0x0
|
|
phy_xaui_tx_polarity_flip_69.0=0x0
|
|
port_init_autoneg_69.0=0
|
|
port_phy_addr_69.0=0x7f
|
|
portmap_69.0=73:40
|
|
portmap_70.0=74:10:i
|
|
portmap_71.0=75:10:i
|
|
portmap_72.0=76:10:i
|
|
serdes_firmware_mode_69.0=2
|
|
xgxs_rx_lane_map_69.0=0x3120
|
|
xgxs_tx_lane_map_69.0=0x3120
|
|
|
|
# Port {xe72, xe73, xe74, xe75} [40G, 4x10G]
|
|
phy_an_c37_73.0=3
|
|
phy_an_c73_73.0=1
|
|
phy_xaui_rx_polarity_flip_73.0=0x0
|
|
phy_xaui_tx_polarity_flip_73.0=0x0
|
|
port_init_autoneg_73.0=0
|
|
port_phy_addr_73.0=0x7f
|
|
portmap_73.0=93:40
|
|
portmap_74.0=94:10:i
|
|
portmap_75.0=95:10:i
|
|
portmap_76.0=96:10:i
|
|
serdes_firmware_mode_73.0=2
|
|
xgxs_rx_lane_map_73.0=0x3120
|
|
xgxs_tx_lane_map_73.0=0x3120
|
|
|
|
# Port {xe76, xe77, xe78, xe79} [40G, 4x10G]
|
|
phy_an_c37_77.0=3
|
|
phy_an_c73_77.0=1
|
|
phy_xaui_rx_polarity_flip_77.0=0x0
|
|
phy_xaui_tx_polarity_flip_77.0=0x0
|
|
port_init_autoneg_77.0=0
|
|
port_phy_addr_77.0=0x7f
|
|
portmap_77.0=89:40
|
|
portmap_78.0=90:10:i
|
|
portmap_79.0=91:10:i
|
|
portmap_80.0=92:10:i
|
|
serdes_firmware_mode_77.0=2
|
|
xgxs_rx_lane_map_77.0=0x3120
|
|
xgxs_tx_lane_map_77.0=0x3120
|
|
|
|
# Port {xe80, xe81, xe82, xe83} [40G, 4x10G]
|
|
phy_an_c37_81.0=3
|
|
phy_an_c73_81.0=1
|
|
phy_xaui_rx_polarity_flip_81.0=0x0
|
|
phy_xaui_tx_polarity_flip_81.0=0x0
|
|
port_init_autoneg_81.0=0
|
|
port_phy_addr_81.0=0x7f
|
|
portmap_81.0=101:40
|
|
portmap_82.0=102:10:i
|
|
portmap_83.0=103:10:i
|
|
portmap_84.0=104:10:i
|
|
serdes_firmware_mode_81.0=2
|
|
xgxs_rx_lane_map_81.0=0x3120
|
|
xgxs_tx_lane_map_81.0=0x3120
|
|
|
|
# Port {xe84, xe85, xe86, xe87} [40G, 4x10G]
|
|
phy_an_c37_85.0=3
|
|
phy_an_c73_85.0=1
|
|
phy_xaui_rx_polarity_flip_85.0=0x0
|
|
phy_xaui_tx_polarity_flip_85.0=0x0
|
|
port_init_autoneg_85.0=0
|
|
port_phy_addr_85.0=0x7f
|
|
portmap_85.0=97:40
|
|
portmap_86.0=98:10:i
|
|
portmap_87.0=99:10:i
|
|
portmap_88.0=100:10:i
|
|
serdes_firmware_mode_85.0=2
|
|
xgxs_rx_lane_map_85.0=0x3120
|
|
xgxs_tx_lane_map_85.0=0x3120
|
|
|
|
# Port {xe88, xe89, xe90, xe91} [40G, 4x10G]
|
|
phy_an_c37_89.0=3
|
|
phy_an_c73_89.0=1
|
|
phy_xaui_rx_polarity_flip_89.0=0x0
|
|
phy_xaui_tx_polarity_flip_89.0=0x0
|
|
port_init_autoneg_89.0=0
|
|
port_phy_addr_89.0=0x7f
|
|
portmap_89.0=109:40
|
|
portmap_90.0=110:10:i
|
|
portmap_91.0=111:10:i
|
|
portmap_92.0=112:10:i
|
|
serdes_firmware_mode_89.0=2
|
|
xgxs_rx_lane_map_89.0=0x3120
|
|
xgxs_tx_lane_map_89.0=0x3120
|
|
|
|
# Port {xe92, xe93, xe94, xe95} [40G, 4x10G]
|
|
phy_an_c37_93.0=3
|
|
phy_an_c73_93.0=1
|
|
phy_xaui_rx_polarity_flip_93.0=0x0
|
|
phy_xaui_tx_polarity_flip_93.0=0x0
|
|
port_init_autoneg_93.0=0
|
|
port_phy_addr_93.0=0x7f
|
|
portmap_93.0=105:40
|
|
portmap_94.0=106:10:i
|
|
portmap_95.0=107:10:i
|
|
portmap_96.0=108:10:i
|
|
serdes_firmware_mode_93.0=2
|
|
xgxs_rx_lane_map_93.0=0x3120
|
|
xgxs_tx_lane_map_93.0=0x3120
|
|
|
|
# Port {xe96} [40G only]
|
|
phy_an_c37_97.0=3
|
|
phy_an_c73_97.0=1
|
|
phy_xaui_rx_polarity_flip_97.0=0x0
|
|
phy_xaui_tx_polarity_flip_97.0=0x0
|
|
port_init_autoneg_97.0=0
|
|
port_phy_addr_97.0=0x7f
|
|
portmap_97.0=61:40
|
|
serdes_firmware_mode_97.0=2
|
|
xgxs_rx_lane_map_97.0=0x2031
|
|
xgxs_tx_lane_map_97.0=0x2031
|
|
|
|
# Port {xe97} [40G only]
|
|
phy_an_c37_98.0=3
|
|
phy_an_c73_98.0=1
|
|
phy_xaui_rx_polarity_flip_98.0=0x0
|
|
phy_xaui_tx_polarity_flip_98.0=0x0
|
|
port_init_autoneg_98.0=0
|
|
port_phy_addr_98.0=0x7f
|
|
portmap_98.0=57:40
|
|
serdes_firmware_mode_98.0=2
|
|
xgxs_rx_lane_map_98.0=0x2031
|
|
xgxs_tx_lane_map_98.0=0x2031
|
|
|
|
# Port {xe98} [40G only]
|
|
phy_an_c37_99.0=3
|
|
phy_an_c73_99.0=1
|
|
phy_xaui_rx_polarity_flip_99.0=0x0
|
|
phy_xaui_tx_polarity_flip_99.0=0x0
|
|
port_init_autoneg_99.0=0
|
|
port_phy_addr_99.0=0x7f
|
|
portmap_99.0=81:40
|
|
serdes_firmware_mode_99.0=2
|
|
xgxs_rx_lane_map_99.0=0x0213
|
|
xgxs_tx_lane_map_99.0=0x0213
|
|
|
|
# Port {xe99} [40G only]
|
|
phy_an_c37_100.0=3
|
|
phy_an_c73_100.0=1
|
|
phy_xaui_rx_polarity_flip_100.0=0x0
|
|
phy_xaui_tx_polarity_flip_100.0=0x0
|
|
port_init_autoneg_100.0=0
|
|
port_phy_addr_100.0=0x7f
|
|
portmap_100.0=85:40
|
|
serdes_firmware_mode_100.0=2
|
|
xgxs_rx_lane_map_100.0=0x0213
|
|
xgxs_tx_lane_map_100.0=0x0213
|
|
|
|
# Port {xe100} [40G only]
|
|
phy_84328_101.0=1
|
|
phy_an_c37_101.0=3
|
|
phy_an_c73_101.0=1
|
|
phy_aux_voltage_enable_101.0=0x1
|
|
phy_ext_rom_boot_101.0=0x0
|
|
phy_line_tx_mode_101.0=1
|
|
phy_rx_polarity_flip_101.0=0x0
|
|
phy_system_tx_mode_101.0=0
|
|
phy_tx_polarity_flip_101.0=0x0
|
|
phy_xaui_rx_polarity_flip_101.0=0x0
|
|
phy_xaui_tx_polarity_flip_101.0=0x0
|
|
port_phy_addr_101.0=0x54
|
|
port_phy_clause_101.0=0x2d
|
|
port_phy_id0_101.0=0x600d
|
|
port_phy_id1_101.0=0x8500
|
|
portmap_101.0=117:40
|
|
serdes_firmware_mode_101.0=1
|
|
xgxs_rx_lane_map_101.0=0x0123
|
|
xgxs_tx_lane_map_101.0=0x0123
|
|
|
|
# Port {xe101} [40G only]
|
|
phy_84328_102.0=1
|
|
phy_an_c37_102.0=3
|
|
phy_an_c73_102.0=1
|
|
phy_aux_voltage_enable_102.0=0x1
|
|
phy_ext_rom_boot_102.0=0x0
|
|
phy_line_tx_mode_102.0=1
|
|
phy_rx_polarity_flip_102.0=0x0
|
|
phy_system_tx_mode_102.0=0
|
|
phy_tx_polarity_flip_102.0=0x0
|
|
phy_xaui_rx_polarity_flip_102.0=0x0
|
|
phy_xaui_tx_polarity_flip_102.0=0x0
|
|
port_phy_addr_102.0=0x50
|
|
port_phy_clause_102.0=0x2d
|
|
port_phy_id0_102.0=0x600d
|
|
port_phy_id1_102.0=0x8500
|
|
portmap_102.0=113:40
|
|
serdes_firmware_mode_102.0=1
|
|
xgxs_rx_lane_map_102.0=0x0123
|
|
xgxs_tx_lane_map_102.0=0x0123
|
|
|
|
# Port {xe102} [40G only]
|
|
phy_84328_103.0=1
|
|
phy_an_c37_103.0=3
|
|
phy_an_c73_103.0=1
|
|
phy_aux_voltage_enable_103.0=0x1
|
|
phy_ext_rom_boot_103.0=0x0
|
|
phy_line_tx_mode_103.0=1
|
|
phy_rx_polarity_flip_103.0=0x0
|
|
phy_system_tx_mode_103.0=0
|
|
phy_tx_polarity_flip_103.0=0x0
|
|
phy_xaui_rx_polarity_flip_103.0=0x0
|
|
phy_xaui_tx_polarity_flip_103.0=0x0
|
|
port_phy_addr_103.0=0x7c
|
|
port_phy_clause_103.0=0x2d
|
|
port_phy_id0_103.0=0x600d
|
|
port_phy_id1_103.0=0x8500
|
|
portmap_103.0=5:40
|
|
serdes_firmware_mode_103.0=1
|
|
xgxs_rx_lane_map_103.0=0x0123
|
|
xgxs_tx_lane_map_103.0=0x0123
|
|
|
|
# Port {xe103} [40G only]
|
|
phy_84328_104.0=1
|
|
phy_an_c37_104.0=3
|
|
phy_an_c73_104.0=1
|
|
phy_aux_voltage_enable_104.0=0x1
|
|
phy_ext_rom_boot_104.0=0x0
|
|
phy_line_tx_mode_104.0=1
|
|
phy_rx_polarity_flip_104.0=0x0
|
|
phy_system_tx_mode_104.0=0
|
|
phy_tx_polarity_flip_104.0=0x0
|
|
phy_xaui_rx_polarity_flip_104.0=0x0
|
|
phy_xaui_tx_polarity_flip_104.0=0x0
|
|
port_phy_addr_104.0=0x78
|
|
port_phy_clause_104.0=0x2d
|
|
port_phy_id0_104.0=0x600d
|
|
port_phy_id1_104.0=0x8500
|
|
portmap_104.0=1:40
|
|
serdes_firmware_mode_104.0=1
|
|
xgxs_rx_lane_map_104.0=0x0123
|
|
xgxs_tx_lane_map_104.0=0x0123
|