75 lines
1.6 KiB
C
75 lines
1.6 KiB
C
/* register offset define */
|
|
#define QSFP_LOW_POWER_REG 0x62
|
|
#define QSFP_RESET_REG 0x72
|
|
#define QSFP_PRESENT_REG 0x82
|
|
#define QSFP_INT_REG 0x92
|
|
#define QSFP_RESET 1
|
|
|
|
unsigned char qsfp_low_power_regs[9][2] = {
|
|
{0x00, 0x00}, //cpld offset, bit mask
|
|
{0x62, 0x01},
|
|
{0x62, 0x02},
|
|
{0x62, 0x04},
|
|
{0x62, 0x08},
|
|
{0x62, 0x10},
|
|
{0x62, 0x20},
|
|
{0x62, 0x40},
|
|
{0x62, 0x80}
|
|
};
|
|
|
|
unsigned char qsfp_reset_regs[9][2] = {
|
|
{0x00, 0x00}, //cpld offset, bit mask
|
|
{0x72, 0x01},
|
|
{0x72, 0x02},
|
|
{0x72, 0x04},
|
|
{0x72, 0x08},
|
|
{0x72, 0x10},
|
|
{0x72, 0x20},
|
|
{0x72, 0x40},
|
|
{0x72, 0x80}
|
|
};
|
|
|
|
unsigned char qsfp_present_regs[9][2] = {
|
|
{0x00, 0x00}, //cpld offset, bit mask
|
|
{0x82, 0x01},
|
|
{0x82, 0x02},
|
|
{0x82, 0x04},
|
|
{0x82, 0x08},
|
|
{0x82, 0x10},
|
|
{0x82, 0x20},
|
|
{0x82, 0x40},
|
|
{0x82, 0x80}
|
|
};
|
|
|
|
unsigned char qsfp_int_regs[33][2] = {
|
|
{0x00, 0x00}, //cpld offset, bit mask
|
|
{0x92, 0x01},
|
|
{0x92, 0x02},
|
|
{0x92, 0x04},
|
|
{0x92, 0x08},
|
|
{0x92, 0x10},
|
|
{0x92, 0x20},
|
|
{0x92, 0x40},
|
|
{0x92, 0x80}
|
|
};
|
|
|
|
unsigned char qsfp_quter_int_regs[2][2] = {
|
|
{0x00, 0x00}, //cpld offset, bit mask
|
|
{0xd0, 0x20}
|
|
};
|
|
|
|
unsigned char qsfp_quter_int_mask_regs[2][2] = {
|
|
{0x00, 0x00}, //cpld offset, bit mask
|
|
{0xd1, 0x20}
|
|
};
|
|
|
|
unsigned char qsfp_modprs_int_regs[2][2] = {
|
|
{0x00, 0x00}, //cpld offset, bit mask
|
|
{0xd0, 0x04}
|
|
};
|
|
|
|
unsigned char qsfp_modprs_int_mask_regs[2][2] = {
|
|
{0x00, 0x00}, //cpld offset, bit mask
|
|
{0xd1, 0x04}
|
|
};
|
|
/* end of register offset define */ |