sonic-buildimage/device/arista/x86_64-arista_7260cx3_64/Arista-7260CX3-D108C8
Neetha John 881796f376
[202012] Adjust 7260 buffer sizes to accomodate extra lossless queues (#11050)
Backport changes from #11018

Signed-off-by: Neetha John <nejo@microsoft.com>

Why I did it
As part of PCBB changes, we need to enable 2 extra lossless queues. The changes in this PR are done to adjust only the reserved sizes on Th2 for the additional 2 lossless queues
Calculations are done based on 40 downlinks for T1 and 16 uplinks for dual ToR

How to verify it
Verified that the rendering works fine on Th2 dut
Unit tests have been updated to reflect the modified buffer sizes when pcbb is enabled. There are existing testcases that will test the original buffer sizes when pcbb is disabled. With these changes, was able to build sonic-config-engine wheel successfully
2022-06-06 18:13:16 -07:00
..
buffers_defaults_t0.j2 [202012] Adjust 7260 buffer sizes to accomodate extra lossless queues (#11050) 2022-06-06 18:13:16 -07:00
buffers_extra_queues.j2 [202012][cherry-pick] Add two extra lossless queues for bounced back traffic (#10715) 2022-06-04 19:25:02 +08:00
buffers_pool_sizes_t0.j2 [202012] Adjust 7260 buffer sizes to accomodate extra lossless queues (#11050) 2022-06-06 18:13:16 -07:00
buffers.json.j2 Improve: buffer configuration infrastructure (#1403) 2018-02-27 12:15:56 -08:00
config.bcm.j2 [Tunnel PFC] Add property for tunnel PFC (#10962) 2022-06-05 22:02:19 -07:00
pg_profile_lookup.ini [devices]: PG headroom change for Arista 7260 (#3600) 2019-10-15 06:03:48 -07:00
port_config.ini [Arista7260CX3] add port speed information to port_config.ini (#1412) 2018-02-27 12:16:15 -08:00
qos.json.j2 [cherry-pick] [202012] Update qos config to clear queues for bounced back traffic (#10608) 2022-06-02 16:29:25 +08:00
sai.profile 7260cx3 DualToR config.bcm support based on DualToR setting in device metadata at boot time (#7168) 2021-04-15 16:12:09 -07:00