a68ce12dd6
- Why I did it A new SKU for MSN4700 Platform i.e. Mellanox-SN4700-V16A96 Requirements: Breakout: Port 1-24: 4x25G(4)[10G,1G] Port 25-28: 2x100G[200G,50G,40G,25G,10G,1G] Port 29-32: 2x200G[100G,50G,40G,25G,10G,1G] Downlinks: 96 (1-24) + 4 (25-28) Uplinks: 4 (29-32) Shared Headroom: Enabled Over Subscribe Ratio: 1:4 Default Topology: T0 Default Cable Length for T1: 5m VxLAN source port range set: No Static Policy Based Hashing Supported: No Additional Details: QoS params: The default ones defined in qos_config.j2 will be applied Small Packet Percentage: Used 50% for traditional buffer model Note: For dynamic model, the value defined in LOSSLESS_TRAFFIC_PATTERN|AZURE|small_packet_percentage is used SKU was drafted under the assumption that the downlink ports uses xcvr's that will only support the first 4 lanes of the physical port they are connected to. Hence for the ports 1-24, the last four lanes are not used Cable Lengths used for generating buffer_defaults_{t0,t1}.j2 values Signed-off-by: Vivek Reddy Karri <vkarri@nvidia.com> |
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x86_64-mlnx_lssn2700-r0 | ||
x86_64-mlnx_msn2010-r0 | ||
x86_64-mlnx_msn2100-r0 | ||
x86_64-mlnx_msn2410-r0 | ||
x86_64-mlnx_msn2700_simx-r0 | ||
x86_64-mlnx_msn2700-r0 | ||
x86_64-mlnx_msn2740-r0 | ||
x86_64-mlnx_msn3420-r0 | ||
x86_64-mlnx_msn3700_simx-r0 | ||
x86_64-mlnx_msn3700-r0 | ||
x86_64-mlnx_msn3700c-r0 | ||
x86_64-mlnx_msn3800-r0 | ||
x86_64-mlnx_msn4410-r0 | ||
x86_64-mlnx_msn4600-r0 | ||
x86_64-mlnx_msn4600c-r0 | ||
x86_64-mlnx_msn4700_simx-r0 | ||
x86_64-mlnx_msn4700-r0 | ||
x86_64-mlnx_x86-r5.0.1400 | ||
x86_64-nvidia_sn2201-r0 | ||
x86_64-nvidia_sn4800_simx-r0 | ||
x86_64-nvidia_sn4800-r0 | ||
x86_64-nvidia_sn5600_simx-r0 |