695652c9d1
This is a 1RU switch with 32 QSFP28 (40G/100G) ports on Broadcom Tomahawk I chipset. CPU used in QFX5200-32C-S is Intel Ivy Bridge. The machine has Redundant and hot-swappable Power Supply (1+1) and also has Redundant and hot swappable fans (5). Signed-off-by: Ciju Rajan K <crajank@juniper.net> Signed-off-by: Ashish Bhensdadia <bashish@juniper.net>
94 lines
2.1 KiB
C
94 lines
2.1 KiB
C
/*
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* Juniper Tmc FPGA register definitions
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*
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* Copyright (C) 2018 Juniper Networks
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* Author: Ashish Bhensdadia <bashish@juniper.net>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef __JNX_TMC_H__
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#define __JNX_TMC_H__
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#define TMC_REVISION 0x00064
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#define TMC_MINOR 0x00068
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#define TMC_SCRATCH 0x00098
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#define TMC_OPTIC_CPLD_MAJOR 0x00104
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#define TMC_OPTIC_CPLD_MINOR 0x00108
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/*
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* I2C Master Block
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*/
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#define TMC_I2C_AUTOMATION_I2C_CONTROL_START 0x07000
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#define TMC_I2C_AUTOMATION_I2C_CONTROL_END 0x07500
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#define TMC_I2C_DPMEM_ENTRY_START 0x10000
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#define TMC_I2C_DPMEM_ENTRY_END 0x13FFC
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#define TMC_LED_CONTROL_START 0x58
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#define TMC_LED_CONTROL_END 0x5B
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/*
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* RE-FPGA block
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*/
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#define TMC_REFPGA_ACCESS_START 0x228
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#define TMC_REFPGA_ACCESS_END 0x233
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#define TMC_I2C_MASTER_NR_MSTRS 16
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#define TMC_I2C_MSTR_MAX_GROUPS 66
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/*
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* TMC GPIO SLAVE Block
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*/
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#define TMC_GPIO_PTP_RESET_START 0x94
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#define TMC_GPIO_PTP_RESET_END 0x97
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#define TMC_GPIO_PTP_CFG_START 0xa4
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#define TMC_GPIO_PTP_CFG_END 0xa7
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#define TMC_GPIO_PTP_DATA_START 0xa8
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#define TMC_GPIO_PTP_DATA_END 0xab
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#define TMC_GPIO_SLAVE0_START 0xf0
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#define TMC_GPIO_SLAVE0_END 0x16b
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#define TMC_GPIO_SLAVE1_START 0x170
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#define TMC_GPIO_SLAVE1_END 0x1eb
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#define TMC_GPIO_SLAVE2_START 0x1f0
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#define TMC_GPIO_SLAVE2_END 0x213
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#define TMC_GPIO_SLAVE3_START 0x280
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#define TMC_GPIO_SLAVE3_END 0x2eb
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#define TMC_GPIO_SFP_SLAVE0_START 0x308
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#define TMC_GPIO_SFP_SLAVE0_END 0x32b
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#define TMC_GPIO_SFP_SLAVE1_START 0x32c
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#define TMC_GPIO_SFP_SLAVE1_END 0x34b
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/*
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* TMC PSU Block
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*/
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#define TMC_PSU_START 0x240
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#define TMC_PSU_END 0x243
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/*
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* TMC SHUTDOWN REG
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*/
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#define TMC_SYS_SHUTDOWN_LOCK 0x254
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#define TMC_SYS_SHUTDOWN 0x250
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/*
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* TMC DS100 MUX Block
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*/
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#define TMC_GPIO_MUX_SLAVE_START 0x26c
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#define TMC_GPIO_MUX_SLAVE_END 0x26f
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#endif /* __JNX_TMC_H__ */
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